Boots – shoes – and leggings
Patent
1991-11-19
1994-04-05
Fleming, Michael R.
Boots, shoes, and leggings
395325, 364DIG1, G06F 900
Patent
active
053013310
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of terminating asynchronous CPU processes at the time of occurrence of an interruption and to a method of reporting CPU-resource-using process-dependent factors generated in the asynchronous CPU processes for use in a CPU which executes some CPU resource using processes with long processing times, asynchronously with instructions while guaranteeing data-dependent relationships of the processes. (Although a process is initiated by an instruction, the process is terminated after the instruction is terminated. After executing the instruction that initiated the process, the CPU initiates execution of a next instruction before termination of the initiated process.) The present invention is especially effective in executing basic processes used in an OS interruption handler asynchronously with instruction execution.
2. Description of the Related Art
In a CPU which executes a CPU-resource-using processes with a long processing time asynchronously with execution of an initiating instruction, partial prior execution of an instruction succeeding a preceding instruction which is long in processing time can be performed by partial prior execution of the succeeding instruction and canceling the effect of the preceding instruction when a program interruption is generated in the initiated by the preceding instruction process. In this case, however, the instruction pipeline of the CPU becomes complicated and the extent of prior execution of the succeeding instruction is limited.
An effective method of improving the CPU's performance without stopping the execution of a simultaneously executable succeeding CPU instruction (bearing no data-dependent relationship with the previous process) when the previous process requires a long processing time time in a CPU-resource, is to execute the CPU-resource-using process with a long processing time asynchronously with the execution of the succeeding instruction. Using this method, a plurality of, CPU-resource-using processes containing more than one asynchronous CPU-resource-using process will be executed at the same time.
In conventional computers, the following methods are used to terminate a CPU-resource-using process when an interruption occurs. There are two types of interruptions: CPU-resource-using process-dependent interruptions; and CPU-resource-using process-independent interruptions.
(1) All CPU-resource-using processes are executed synchronously with instructions. When a CPU-resource-using process-dependent interruption factor is detected as a result of an execution of an instruction, a corresponding CPU-resource-using process-dependent interruption is generated prior to the execution of the next instruction after the termination of the execution of the instruction. Only when no CPU-resource-using process-dependent interruption is detected at the execution of the last instruction and a CPU-resource-using process-independent factor is present, a corresponding CPU-resource using-process-independent interruption is generated.
In the situation where all the CPU-resource-using processes initiated prior to an interruption have been terminated at the time of the occurrence of the interruption, an interruption handler is easy to construct. In the case of an interruption for a necessary CPU-resource-using process-dependent factor, an original program can be resumed after proper processing by the interruption handler.
In the case of the previously described situation in a process (instruction) executing system, however, the execution of a succeeding CPU-resource-using process cannot be terminated during the execution of a CPU-resource using process with a long execution time, thus degrading the performance of the CPU.
(2) A unit (for example, a floating-point arithmetic unit) performs input/output operations on some of the CPU resources and asynchronously executes processes (asynchronous CPU-resource-using processes) which are initiated by instructions and executed asynchronously with
REFERENCES:
patent: 4385365 (1983-05-01), Hashimoto et al.
patent: 4423480 (1983-12-01), Bauer et al.
patent: 4456970 (1984-06-01), Catiller et al.
patent: 4716523 (1987-12-01), Burrus, Jr. et al.
patent: 4758950 (1988-07-01), Cruess et al.
patent: 4761732 (1988-08-01), Eldumiati et al.
patent: 4788655 (1988-11-01), Nakayama et al.
patent: 4897810 (1990-01-01), Nix
patent: 4959782 (1990-09-01), Tulpule et al.
patent: 5155809 (1992-10-01), Baker et al.
Bhandarkar et al., "Vector Extensions to the VAX Architecture", 35th IEEE Computer Society International Conference, Compcon Spring '90, Feb. 1990, San Francisco, pp. 120-126.
Iacobovici, S., "A Pipelined Interface for High Floating-point Performance with Precise Exceptions", IEEE Micro, vol. 8, No. 3, Jun. 1988, New York, pp. 77-87.
Van de Goor, A. J., "Computer Architecture and Design", Addison-Wesley Publishing Co., 1989, pp. 424-427.
Supplementary European Search Report, The Hague, Aug. 26, 1993.
Nakayama Yozo
Ueno Haruhiko
Fleming Michael R.
Fujitsu Limited
Hafiz Tariq R.
LandOfFree
Interruption handling system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Interruption handling system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interruption handling system will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-520217