Interrupt steering in computing devices to effectuate...

Details Interrupt steering in computing devices to effectuate... Interrupt steering in computing devices to effectuate...

2007-11-27

2007-11-27

Auve, Glenn A. (Department: 2111)

Electrical computers and digital data processing systems: input/

Interrupt processing

Source or destination identifier

C710S260000, C710S261000, C710S263000, C710S048000

Reexamination Certificate

active

11297992

ABSTRACT:
A computer device, an input/output (“I/O”) communication subsystem, a chipset and a method are disclosed for implementing interrupt message packets to facilitate peer-to-peer communications between a device controller and a coprocessor. Advantageously, the various embodiments of the invention obviate a requirement for specialized circuitry on a motherboard to establish peer-to-peer communications. In one embodiment, an I/O communication subsystem includes a bus interface for coupling the I/O communication subsystem to a general-purpose bus. It also includes a device controller being configured to generate an interrupt as an interrupt message packet for a coprocessor, which, in turn, interrupts processing functions that otherwise are performed by the host processor. The device controller can reside either internal or external to the I/O communication subsystem.

REFERENCES:
patent: 2004/0225790 (2004-11-01), George et al.
patent: 2005/0033895 (2005-02-01), Lueck et al.
patent: 2007/0067534 (2007-03-01), Butler et al.
PCI Express Base Specification Revision 1.1; PCI-SIG; pp. 1-9 and 273-275; Mar. 28, 2005.
Budruk, Ravi; Anderson, Don; and Shanley, Tom; PCI Express System Architecture; MindShare, Inc.; Chapter 9: Interrupts; Feb. 2005.
Intel®, “MROMB Design Considerations using the Intel® 80303 I/O Processor,” Order No. 273593-002, Sep. 2002, pp. 1-15.

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