Interrupt-processing system for shortening interrupt latency...

Details Interrupt-processing system for shortening interrupt latency... Interrupt-processing system for shortening interrupt latency...

2006-05-23

2006-05-23

Vo, Tim (Department: 2111)

Electrical computers and digital data processing systems: input/

Interrupt processing

C710S266000, C711S215000, C711S206000, C711S113000

Reexamination Certificate

active

07051138

ABSTRACT:
The invention relates to a data processing system which comprises a memory module and a microprocessor. The memory modules comprise at least one low-speed memory and one high-speed memory; both store an interrupt vector table individually for recording the entry instruction of interrupt service routines. The microprocessor comprises a central processing unit (CPU) and a memory controller with a re-addressing device. Once an interruption occurs, the CPU generates and sends an interrupt vector address to the memory controller. If the vector is located in the range of interrupt vector table, the re-addressing device sends an enable signal to the high-speed memory to enable the CPU to fetch the entry instruction of interrupt service routines from the high-speed memory, not from the pre-determined low-speed memory. Hence, the interrupt latency is reduced.

REFERENCES:
patent: 6378023 (2002-04-01), Christie et al.
patent: 6601122 (2003-07-01), Broberg et al.
patent: 6704863 (2004-03-01), Paul et al.
patent: 6889279 (2005-05-01), Godfrey

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