Interrupt processing in a data processing system

Details Interrupt processing in a data processing system Interrupt processing in a data processing system

2005-05-10

2005-05-10

Vo, Tim (Department: 2112)

Electrical computers and digital data processing systems: input/

Interrupt processing

C710S263000, C712S244000

Reexamination Certificate

active

06892260

ABSTRACT:
The present invention relates generally to interrupt processing. One embodiment relates to a method for executing an interrupt in a data processing system including fetching a conditional store instruction that is conditional upon a reservation, receiving notice that an interrupt is pending, invalidating a reservation in response to receiving the notice, and processing the interrupt. Invalidating the reservation allows the conditional store instruction to finish in a predetermined amount of time and properly update an architectural state of the processor. Therefore, interrupt latencies (the amount of time between receiving and processing an interrupt) corresponding to the conditional store instruction can be bounded. The method may be used in a single processor or multi-processor data processing system, wherein each processor includes a reservation register. Furthermore, each processor may include both a completion unit for storing instructions in the order they are issued and a store queue within a load/store unit.

REFERENCES:
patent: 5193167 (1993-03-01), Sites et al.
patent: 5742785 (1998-04-01), Stone et al.
patent: 6076183 (2000-06-01), Espie et al.
patent: 6473850 (2002-10-01), Cheong et al.
patent: 20020087769 (2002-07-01), McKenney et al.
patent: 20030070021 (2003-04-01), Joy et al.

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