Interrupt pacing in data transfer unit

Details Interrupt pacing in data transfer unit Interrupt pacing in data transfer unit

1999-08-27

2003-09-02

Lefkowitz, Sumati (Department: 2833)

Electrical computers and digital data processing systems: input/

Interrupt processing

Interrupt inhibiting or masking

C710S266000

Reexamination Certificate

active

06615305

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to data transfer and processing within a computer system.
BACKGROUND OF THE INVENTION
An exemplary data transfer unit
10
and CPU
20
are depicted in FIG.
1
. The data transfer unit
10
transfers data as instructed by the CPU
20
. When the data transfer unit has completed a data transfer (an event) the CPU is interrupted
30
to process the data. In a typical computer system, it is common for a CPU
20
to receive and process a huge number of interrupts. Due to the time and resources necessary to process an interrupt, frequent interrupts often result in reduced CPU
20
performance. It is therefore desirable to reduce the number of CPU interrupts necessary to transfer data within a system.
SUMMARY OF THE INVENTION
In general, in one aspect, the invention features a method for controlling (pacing) the number of interrupts generated by a data transfer unit to a CPU. Data transfers (events) from a data transfer unit are monitored and recorded before they reach the CPU. When the number of data transfers reaches a defined threshold value, an interrupt is generated to the CPU which allows it to acknowledge and process the data transfers prior to the interrupt.
Another implementation of the invention may include a timing method for generating interrupts in conjunction with the pacing method. The method includes defining a time value to specify the minimum or maximum amount of time between interrupts.
In general, in another aspect, the invention features an apparatus for controlling (pacing) the number of interrupts generated by a data transfer unit to a CPU. The apparatus includes a pacing counter which contains a control unit, a threshold register, event register, and comparator. The control unit monitors and counts events as they are generated by the data transfer unit and also receives the count of events already acknowledged by the CPU. The threshold register is set at a defined value, corresponding to the number of events at which an interrupt will be generated. The event register counts the number of events generated by the data transfer unit. The comparator compares the number of events generated with the defined threshold value, and when the number of generated events corresponds to the threshold value, it generates an interrupt to the CPU.
Other implementations may include the following advantages. A timing apparatus may be used in conjunction with the pacing apparatus. The timing apparatus may be set to specify an amount of time, including a minimum or maximum time, between interrupts. An OR gate may be used to accommodate both the pacing and timing apparatuses and prevent the transmission of simultaneous interrupts, separately generated by each apparatus.
A preset number of data transfers can be thus effected before a CPU is interrupted. The number of interrupts a CPU must process is thus limited, allowing for greater CPU efficiency and performance.


REFERENCES:
patent: 5659758 (1997-08-01), Gentry et al.
patent: 5708814 (1998-01-01), Short et al.
patent: 5913071 (1999-06-01), Macomber
patent: 5933613 (1999-08-01), Tanaka et al.
patent: 5943479 (1999-08-01), Klein et al.
patent: 6012121 (2000-01-01), Govindaraju et al.
patent: 6189066 (2001-02-01), Lowe et al.
patent: 6189067 (2001-02-01), Lowe et al.
patent: 6192440 (2001-02-01), Lowe et al.
patent: 6345345 (2002-02-01), Yu et al.
patent: 6351785 (2002-02-01), Chen et al.

Affiliated with

Also associated with

Rating

Interrupt pacing in data transfer unit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Interrupt pacing in data transfer unit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interrupt pacing in data transfer unit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3054750