Electrical computers and digital data processing systems: input/ – Interrupt processing – Interrupt inhibiting or masking
Reexamination Certificate
1999-03-18
2001-04-17
Thai, Xuan M. (Department: 2181)
Electrical computers and digital data processing systems: input/
Interrupt processing
Interrupt inhibiting or masking
Reexamination Certificate
active
06219744
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an interrupt masker for use in an interrupt handler, and more particularly to an interrupt masker having the capability to handle double-edge interrupt request signals.
BACKGROUND ART
Many computer systems are designated to interface with one or more peripheral devices. A computer system typically includes a central processing unit (CPU) connected to a system bus having data, address, and control lines. The bus is connected to other computer system components, such as program memory, and also to peripheral devices via a suitable interface. The interface may include interface devices for translating voltages or signal formats for compatibility between the computer system and the peripheral devices. Suitable interface connectors are often employed. Communication between the CPU and the peripheral devices can include sensory or command information. Specifically, a peripheral device acting as a sensor may produce data signals indicative of parameters the peripheral sensing device is sensing, such as temperature, voltage, or other parameters. The data signals may be translated to a suitable form and read through the interface by the CPU to provide the CPU with needed data regarding the sensed parameters. Alternatively, the peripheral devices may be controllers. the CPU commands a peripheral controlling device by writing suitable commands through the interface to the peripheral controlling device. The device then takes suitable action in accordance with the command.
In a system including a plurality of peripheral devices, frequent or continuing communication between the CPU and the peripheral devices is often necessary. Various schemes have been used for keeping the CPU in touch with the peripheral devices. A first scheme is called polling. In a polling system, the CPU executes a polling routine at intervals of time. Typically, a hardware timer will cause the CPU to execute the polling routine periodically. During the polling routine, the CPU reads information from the peripheral devices indicating whether the status of a sensed parameter has changed or whether there is a need to send a command to the peripheral device. Depending on the information received from a given peripheral device during the polling routine, the CPU takes appropriate action, such as sending commands to the peripheral device or updating a record of the status of the peripheral device stored in computer system memory. Polling is commonly used in computer systems which interface with a large number of peripheral devices. However, polling has the disadvantage that the polling routine must be executed frequently, thereby consuming a large amount of CPU processing time. in many instances, the status information read from the peripheral devices indicates that no action is necessary. Thus, the time spent executing the polling routine in retrospect proves to be unproductive. In computer system involving a great deal of activity or real-time applications, the time spent repeating the polling routine can reduce processing efficiency.
As an alternative to polling, computer systems often service peripheral devices by means of interrupts. In an interrupt system, a peripheral device sends a signal called an interrupt request when a condition is detected requiring some type of action by the CPU. Many CPUs are designed to include interrupt request input lines. A CPU having such an interrupt request input responds to a predetermined voltage signal on the interrupt request line by executing an interrupt service routine. Thus, an interface between a CPU and a peripheral device can include circuitry which detects a change of status in the peripheral device for which service is required and provides a suitable interrupt request signal to the CPU.
Interrupt handling circuits are well known in the prior art to control processing units upon receiving interrupt request signals from peripheral devices. Conventional interrupt handlers are either edge-triggered or level-triggered. When edge-triggered only one type of edges of the interrupt request signal, i.e. a high-to-low or a low-to-high transition, is detected.
The edge setting is done at the initialization of the system, by configurating all the inputs of the interrupt handler according to the corresponding attached peripheral device. These programmable interrupt handlers have the drawback that each input is definitively configurated in one way, and is maintained until the process is ended.
In the present applications, it is mandatory that during the system operating, an interrupt request signal be indifferently processed on one type of transition or the other without disturbing the system operating cycle or without generating any undesirable glitches.
In known solutions, the interrupt request signal is inverted within an input port circuit of the interrupt handler upon reception of a polarity control signal which is generated by the processing unit each time an opposite polarity is requested. The interrupt handler therefore operates as accepting both edges of the interrupt request signal.
Unfortunately the polarity control signal generates a glitch which may be misinterpreted by the interrupt handler as being an occurrence of the interrupt request signal. To resolve this problem, software solutions have been implemented within the processing unit program to operate a Mask Interrupt Register which enables the valid interrupt requests and inhibits the unvalid ones. The drawback of such solution is that a very complex algorithm is needed to control the interrupt handler. Furthermore, several cycles are needed to perform the controled inversion function.
Another known solution is to implement an inhibit circuit within the input port circuit of the interrupt handler which is activated by the processing unit before the inversion control signal occurs and which is maintained several cycles to ensure that the inversion function is performed. However, the drawback of such solution is that the system performance is decreased.
Therefore there is a need for an efficient glitch free circuit that can change dynamically the edge polarity of the interrupt request signals. Such circuit has to be able to perform the edge polarity inversion within a processing unit cycle time.
SUMMARY OF THE INVENTION
It is an object of this invention to provide an interrupt handler for use in a computer system comprising a central processing unit connected by a computer system bus to a memory and to the interrupt handler. The interrupt handler receives interrupt request signals in the form of edge detection or level assertion and is able to handle both type of edge transitions of the interrupt request signal. The interrupt handler comprises an interrupt masker circuit comprising interrupt detection means for detecting edge transitions of the interrupt request signal. The interrupt masker also comprises a polarity detection means for detecting edge transitions of a polarity control signal which is inverted for each inversion polarity request. A,filtering means which is coupled to the interrupt detection means and to the polarity detection means generates an interrupt request pulse according to the assertion of the polarity control signal. The interrupt request pulse is generated in response of either rising or falling edge transitions of the interrupt request signal.
It is another object of the invention to provide an interrupt masker free of glitches.
In a preferred embodiment, the arrangement of the interrupt masker is such that the interrupt detection circuit detects one type of edge transition of the interrupt request signal while the polarity detection circuit detects both type of edge transitions of the polarity control signal. The polarity detection circuit further includes an inversion logic circuit responsive to the interrupt request signal and to the polarity control signal for inverting the edge transition of the interrupt request signal when the polarity control signal is asserted.
In an alternate embodiment, the interrupt detection circuit detects
Boudon Gerard
Bredin Francis
Proust Jean-Michel
Augspurger Lynn L.
International Business Machines - Corporation
Thai Xuan M.
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