Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
1999-11-22
2003-04-01
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C709S241000, C710S260000, C710S261000, C710S262000, C710S263000
Reexamination Certificate
active
06543000
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to an interrupt management system for managing interrupts in a processor control system.
BACKGROUND OF THE INVENTION
Many real time processor controlled systems contain programmable down-counters which count down from a predetermined value and on reaching zero generate an interrupt request signal. The down-counter then resets to the original predetermined value and begins decrementing again.
This is typically used in real time processor controlled systems to generate interrupts at fixed periods, during which periods time dependent functions within the real time system are performed.
Although the programmable down-counters allow the interrupts to be accurately generated at each predetermined period, the time taken for those interrupts to be completed i.e. serviced, by the real time system or processor controlling the real time system, can vary greatly. In extreme cases this time delay may exceed the predetermined period of the down-counter, causing one or more subsequent interrupts to be missed by the system.
In order to maintain the reliability of the system, it is desirable to detect such extreme cases in order to allow error handling and to produce appropriate warnings. It is also desirable to know the actual time delay for an interrupt to be serviced.
SUMMARY OF THE INVENTION
The object of embodiments of the present invention is to provide an interrupt management system which is capable of providing the above outlined advantages and overcoming the identified problems of known interrupt systems, in particular so that it is possible to ascertain when an interrupt has been missed and the delay in servicing an interrupt
According to the present invention there is provided an interrupt management system comprising:
a first timer having an input coupled to receive a clock signal and arranged to produce an interrupt request signal at the expiry of a predetermined time period;
a second timer having an input coupled to receive said clock signal and being arranged to hold a count value representing an interrupt service delay;
a processor arranged to receive said interrupt request signal and operable to generate an interrupt serviced signal when the corresponding interrupt has been serviced; and
a controller arranged to receive said interrupt serviced signal from the processor and the count value from the second timer to determine whether an interrupt request has been missed.
According to the present invention there is also provided a method of managing interrupts comprising:
producing an interrupt request signal at the expiry of a predetermined time period in accordance with a system clock;
generating a count value representing an interrupt service delay from said system clock;
generating an interrupt serviced signal when the interrupt request has been serviced; and
determining from the timing of the interrupt service signal and the count value whether an interrupt request has been missed.
A preferred embodiment of the present invention will now be described in further detail with reference to the following figures.
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Lee Thomas
Patel Nitin C.
STMicroelectronics Limited
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