Electrical computers and digital data processing systems: input/ – Interrupt processing
Reexamination Certificate
1998-06-12
2001-05-22
Banankhah, Majid A. (Department: 2151)
Electrical computers and digital data processing systems: input/
Interrupt processing
C710S264000, C710S266000, C709S241000, C709S241000
Reexamination Certificate
active
06237058
ABSTRACT:
BACKGROUNDS OF THE INVENTION
1. Field of the Invention
The present invention relates to an interrupt load distribution for providing optimal distribution of load within a shared bus type multiprocessor system by determining the load status of individual processors and accordingly scheduling interrupt requests generated at I/O, communication or other devices, and an interrupt load distribution method.
2. Description of the Related Art
Basic methods for controlling distribution of load of interrupt processes in a multiprocessor system include a method in which the operating system notifies the hardware of the priorities of processes being executed by individual processors at synchronized points and causes the processor executing the lowest-priority process to carry out an interrupt process, a method in which an interrupt request is issued to all the processors and the processor that has responded to the request the earliest is made to carry out the interrupt process, a method in which the processor that has received an interrupt request notifies the hardware of the next processor to be interrupted according to the round robin or other logic and thus an interrupt process is carried out sequentially, a method in which a processor in an idle state prompts the hardware to allocate an interrupt request to itself, and a method that combines these methods as necessary.
One prior art for choosing the most appropriate among multiple processors in ensuring optimal load balance within the entire system and making the processor to carry out an interrupt process is disclosed in Japanese Patent Laying-Open (Kokai) No. Heisei 8-329022, entitled “System for Controlling Distribution of I/O Process Load in Multiprocessor System.” The art recited in this literature consists of I/O processing processes for performing various I/O processes by being scheduled by a scheduler individually to different operation processors, a request ticket table for designating an I/O processing process to perform a requested I/O process, a return ticket table which is provided for each I/O processing process for registering an I/O action to be processed by that I/O processing process, and an I/O process load distributing part for referring to the request ticket table when an I/O process is requested and registering such I/O process into the return ticket table specified in the request ticket table, thereby achieving well-balanced control of load distribution.
As stated above, in conventional shared bus type multiprocessor systems, greater weight is given to distributing interrupt processes depending on such information as the number of interrupt processes or according to the round robin scheduling or otherwise to distributing interrupt processes among idle-state processors detected, rather than to responding to the running status of applications or the state of the operating system that changes from one moment to the next. These methods have not necessarily been effective in distributing interrupt load since they may fail to achieve good balance between processor load caused by processor binds executed by applications and interrupt load, resulting in a possible decrease in the execution speed of applications.
Also, a scheduling policy for distributing interrupt load that is incorporated in an operating system is fixed, which makes it difficult to change the scheduling policy flexibly and easily according to the running status of applications or the state of the operating system on respective user systems.
Furthermore, the system for controlling distribution of I/O process load disclosed in Japanese Patent Laying-Open (Kokai) No. Heisei 8-329022 uses response times for I/O processes as a basis of considering load balance, leaving the running status of applications or the state of the operating system unconsidered, and therefore an improvement in application throughput or system performance cannot necessarily be expected.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an interrupt load distribution system for a shared bus type multiprocessor system, which can minimize a decrease in applications' execution speed and achieve an improved system throughput by performing re-scheduling according to the running status of applications and the state of the operating system that changes from one moment to another to ensure optimum distribution of interrupt load and thereby to achieve good balance between processor load and interrupt load, and an interrupt load distribution method for this system.
Another object of the present invention is to provide an interrupt load distribution system for a shared bus type multiprocessor system, which can improve system performance by customizing an interrupt schedule according to the running status of applications and the state of the operating system on respective user systems and optimizing the distribution of interrupt load.
According to the first aspect of the invention, an interrupt load distribution system for determining the status of load for each processor in a shared bus type multiprocessor system, scheduling interrupt requests that are generated, and distributing load within the system, comprises
processor statistical information table for storing processor statistical information, consisting of processor activity ratios under the use by the operating system, processor activity ratios under the use by processes executing under a processor bind, and number of processes requesting a bind from each processor,
interrupt schedule information table for storing interrupt schedule information which represents a basic rule for distributing interrupt load within an appropriate range,
interrupt scheduling means for referring to information in the processor statistical information table and the schedule information table at fixed time intervals and re-scheduling interrupt load distribution as necessary to achieve appropriate distribution, and
notifying means incorporating an interrupt notification destination information table that stores information concerning the destination to which an interrupt is to be notified, which is updated during re-scheduling by the interrupt scheduling means, for notifying the designated processor of an interrupt request based on information in the interrupt notification destination information table.
In the preferred construction, the interrupt scheduling means may comprise resident-type system processes that are not affected by the status of system load.
In the preferred construction, the interrupt schedule means determines whether re-scheduling of interrupt load distribution is required or not by comparing processor statistics information in the processor statistical information table with pre-determined criterion values, when it determines that re-scheduling is required, determines a schedule within an appropriate range based on schedule information in the interrupt schedule information table, and notifies interrupt notification information to the interrupt notifying means in accordance with the schedule thus determined, and
the interrupt notifying means registers the interrupt notification information in the interrupt notification destination information table in response to notification from the interrupt scheduling means, and notifies the designated processor of an interrupt based on the information concerning destination of interrupt notification.
In the preferred construction, the processor statistical information table is updated on condition that an clock interrupt of the operating system or one or more point in the code of the operating system has been executed, and the processor statistical information table and the interrupt schedule information table allow a supervisor, a privileged user, to refer to and modify processor statistical information and interrupt schedule information by issuing a supervisor call.
In another preferred construction, the interrupt schedule information table has entries corresponding to different interrupt levels, and stores, as the interrupt schedule information, at least interrupt resource,
Banankhah Majid A.
Foley & Lardner
NEC Corporation
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