Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2006-11-28
2006-11-28
Beausoliel, Robert (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S006130, C714S021000, C714S034000, C714S048000, C714S049000, C710S260000
Reexamination Certificate
active
07143311
ABSTRACT:
A data processor formed on a single integrated circuit and capable of connection to an external memory, the data processor including: a central processing unit; a local memory including a debug memory area; a plurality of interrupt inputs; an interrupt handler coupled to the interrupt inputs for interrupting the central processing unit in response to interrupt signals received on the interrupt inputs, and being arranged to periodically store in the debug memory area of the local memory data indicative of the status of the interrupt handler; the data processor being adapted to, after having been reset, perform a start-up routine including the step of outputting the contents of the debug memory area to the external memory.
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Beausoliel Robert
Jenkens & Gilchrist P.C.
Puente Emerson
STMicroelectronics Limited
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