Interrupt generation in a bus system

Details Interrupt generation in a bus system Interrupt generation in a bus system

2006-05-30

2006-05-30

Perveen, Rehana (Department: 2112)

Electrical computers and digital data processing systems: input/

Interrupt processing

Interrupt queuing

C710S260000, C710S242000, C710S266000

Reexamination Certificate

active

07054975

ABSTRACT:
The present invention relates to a bus system comprising a first and second station (10, 14) coupled via a bus (12) for transferring data and control signals, the bus (12) operating according to a protocol in which the first station (10) repeatedly sends requests (200, 210, 220, 230) for data to the second station, the second station (14) responding to each request (200, 210, 220, 230) by sending a message with a data item or sending a negative acknowledge signal (24), wherein the second station (14) comprises:an interruptable processor (15) for generating data items;a first in first out buffer (160) coupled between the processor (15) and the bus (12), for buffering data items for successive messages in a first in first out order, the processor (15) being programmed to start writing the data items to the buffer (160) in response to an interrupt (204, 234);a bus interface (162) arranged to handle the protocol, sending data items from the buffer (160) in the messages, the bus interface (162) sending an interrupt to the processor (15) in response to selected ones of the requests (200, 210, 220, 230), when the buffer is empty and no interrupts have yet been generated since the processor has written into the buffer.

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