Electrical computers and digital data processing systems: input/ – Interrupt processing
Reexamination Certificate
2000-06-21
2003-06-17
Auve, Glenn A. (Department: 2189)
Electrical computers and digital data processing systems: input/
Interrupt processing
C710S261000, C710S262000, C710S263000, C710S264000, C710S265000, C710S266000, C710S267000, C710S268000, C710S269000
Reexamination Certificate
active
06581119
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an interrupt controller preferably used to provide a microcomputer capable of implementing multiple interrupt, and also relates to a microcomputer incorporating this interrupt controller.
In addition to a CPU and memories, a general microcomputer is associated with peripheral circuits, such as an A/D converter, a timer, and a PWM (pulse width modulation) waveform generating circuit. In transmitting data from the CPU to these peripheral circuits and in receiving the data from these peripheral circuits to the CPU, interrupt is used as one interfacial means. A high-performance microcomputer is usually associated with a plurality of peripheral circuits each sending an interrupt request to the CPU. In such a case, there is a possibility that the high-performance microcomputer simultaneously receives a plurality of interrupt requests. To manage such overlapping of interrupt requests, the high-performance microcomputer comprises an interrupt controller interposed between the CPU and each of the peripheral circuits.
For example, the interrupt controller operates in synchronism with the CPU under a same or common clock. The interrupt controller collectively administrates all of the interrupt requests. The interrupt controller arranges these multiple interrupt requests into one signal, which is an interrupt request signal sent to the CPU. This interrupt request signal is hereinafter referred to as a CPU interrupt request signal which differs from an interrupt request signal sent from each peripheral circuit to the CPU. The CPU has an interrupt input terminal receiving the CPU interrupt request signal thus outputted from the interrupt controller.
More specifically, when the interrupt controller receives a plurality of interrupt request signals simultaneously from peripheral circuits, the interrupt controller selects an interrupt request having a highest priority. Then, the interrupt controller produces a vector address corresponding to the selected interrupt processing. Meanwhile, the interrupt controller sends the above-described CPU interrupt request signal to the CPU. When the CPU receives the CPU interrupt request signal, the CPU waits for a delay time which is required for the CPU to prepare the interrupt. After the delay time has passed, the CPU sends a response signal to the interrupt controller. The response signal indicates that the preparation for the interrupt has been accomplished. At the same time, the CPU reads the vector address produced from the interrupt controller. Then, the CPU executes the interrupt processing which is stored in an area designated by this vector address.
In this manner, the interrupt controller outputs the CPU interrupt request signal to cause the CPU to implement the interrupt processing requested by the peripheral circuit. When the CPU is presently implementing other interrupt processing, it is necessary to make the CPU suspend the presently running interrupt processing. However, if the CPU automatically suspends every interrupt processing being presently executed in response to each CPU interrupt request signal sent from the interrupt controller, there will be a possibility that the suspended interrupt processing may have a priority higher than that of the interrupt processing designated by the entered CPU interrupt request signal.
Accordingly, in performing the conventional multiple interrupt, the interrupt controller compares the priority of the interrupt processing presently running in the CPU with the priority of the interrupt processing requested by the peripheral circuit. Then, the interrupt controller sends the CPU interrupt request signal to the CPU only when the priority of the interrupt processing requested by the peripheral circuit is higher than the priority of the interrupt processing presently running in the CPU.
However, in comparing the priority of the interrupt processing presently running in the CPU with the priority of the interrupt processing requested by the peripheral circuit, it is definitely necessary for the interrupt controller to recognize the priority of the interrupt processing presently running in the CPU. To this end, the conventional CPU administrates (memorizes) the priority of the interrupt processing presently running in the CPU. When the interrupt controller receives an interrupt request from a peripheral circuit, the interrupt controller receives the priority of the presently running interrupt processing from the CPU and compares it with the priority of the interrupt processing requested by the peripheral circuit.
Meanwhile, when the CPU receives the CPU interrupt request signal from the interrupt controller during execution of the interrupt processing, the CPU suspends the presently running interrupt processing. The CPU temporarily transfers (i.e., stacks) the data necessary in restarting the suspended interrupt processing to an external storage medium, such as RAM. The processing data necessary in restarting the suspended interrupt processing is, for example, a program counter value and a flag processing state or the like. Similarly, the CPU transfers (i.e., stacks) the level information representing the priority of the suspended interrupt processing to the same external storage medium. Thereafter, the CPU executes the newly request interrupt processing in accordance with the vector address read out from the interrupt controller. When the requested interrupt processing is accomplished, the CPU obtains the stacked information from the external storage medium and restarts the suspended interrupt processing based on the obtained information.
As described above, according to the conventional microcomputer executing the multiple interrupt to the CPU, the CPU itself manages (memorizes) the priority of the interrupt processing being presently executed in the CPU. Accordingly, when the CPU suspends the presently running interrupt processing, the CPU temporarily transfers (stacks) the information necessary in restarting the suspended interrupt processing into RAM or a comparable storage medium. In this case, in addition to the information necessary to restart the suspended interrupt processing, the CPU can transfer (stack) the priority of the suspended interrupt processing into the same storage medium. Thus, administrating the priority of the suspended interrupt processing can be easily done by the CPU.
However, to possess such a priority administrating function, the CPU needs to have a component (i.e., register) which stores the priority of the presently running interrupt processing. This significantly enlarges the circuit scale of the CPU.
In some cases, a same spec CPU may be commonly used in constituting a microcomputer requiring no multiple interrupt and in constituting a microcomputer requiring the multiple interrupt. In such cases, if the commonly used CPU has the above-described priority storing register, the circuit scale of the CPU will be too much large for the microcomputer requiring no multiple interrupt. An effective downsizing cannot be realized for this microcomputer. Furthermore, in this case, for the microcomputer requiring no multiple interrupt, its cost unnecessarily increases due to use of the CPU having unnecessary functions.
To enhance the usability of CPU, it is necessary to enlarge the capacity of the register (in other words, the bit number of the register) so that all of the priority data can be stored in the register even if a large number of interrupt requests are generated from peripheral circuits and the data length (i.e., bit number) of the priority being set for each interrupt request becomes large. Accordingly, if required to use a same conventional CPU for various microcomputers whose purposes are different from each other, the circuit scale of this conventional CPU needs to become large. In other words, the microcomputer cannot be downsized.
SUMMARY OF THE INVENTION
The present invention has an object to provide an interrupt controller which makes it possible to use a same or common spec CPU for various microcomputers rega
Ishihara Hideaki
Maeda Kouichi
Noda Sinichi
Auve Glenn A.
Denso Corporation
Posz & Bethards, PLC
Vu Trisha
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