Interrupt controller

Details Interrupt controller Interrupt controller

1999-11-09

2003-06-17

Thai, Xuan M. (Department: 2181)

Electrical computers and digital data processing systems: input/

Interrupt processing

Interrupt inhibiting or masking

C710S260000

Reexamination Certificate

active

06581120

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an interrupt controller for a Micro Controller Unit (MCU), and more particularly, to an interrupt controller which can efficiently execute an interrupt service.
2. Background of the Related Art
In general, an interrupt is a pausing of the execution of a first program to execute another program. When a condition occurs that requires an interruption, the first program is temporarily stopped, and operating control jumps to a different address. Then, an interrupt processing program accessible from the different address is executed. Upon completion of the interrupt processing program, the control returns to the first (interrupted) program, and execution of the first program resumes. Accordingly, effective program processing of simultaneously operated input and output devices can be achieved with effective on-line processing. Related art interrupt controllers often manage numerous type of interrupts, such as input/output completion interrupts, program interrupts, monitoring interrupts and fault interrupts.
FIG. 1
illustrates a system including a related art interrupt controller
3
connected to peripheral devices
2
and to a CPU
1
. The interrupt controller
3
is operative between the, CPU
1
and the peripheral devices
2
.
As shown in
FIG. 1
, the related art interrupt controller
3
is provided with an interrupt mask register
4
for receiving and storing interrupt on/off instructions from the CPU
1
. An interrupt priority register
5
receives and stores interrupt priority instructions from the CPU
1
. An interrupt mask circuit unit
6
selectively receives, and forwards interrupt generating signals, such as INT
0
, INT
1
, INT
2
, . . . INTn, from the peripheral devices
2
in response to an interrupt on/off instruction from the interrupt mask register
4
.
A priority determining circuit unit
7
receives the interrupt generating signals from the interrupt mask circuit unit
6
, determines priorities of the interrupt generating signals in response to the interrupt priority instruction from the interrupt priority register
5
, and forwards an interrupt priority signal to an interrupt terminal at the CPU
1
. An interrupt status register
9
stores information of an interrupt signal from a source peripheral device
2
forwarded from the priority determining circuit unit
7
. A bus interface circuit unit
8
inputs and outputs an address signal between the CPU
1
and the interrupt controller
3
. A buffer unit
10
buffers a data signal from the CPU
1
to the interrupt controller
3
. Here, each register is connected to an internal data bus.
FIG. 2
illustrates a sequence diagram showing a related art method for controlling an interrupt. As shown in
FIG. 2
, interrupt signals INT
0
, INT
1
, - - - , INTn, generated in different peripheral devices
2
, are output to the interrupt mask circuit unit
6
. However, the interrupt signals generated in the peripheral devices
2
, that are not acceptable to the interrupt mask circuit unit
6
based on interrupt on/off instructions stored in the interrupt mask register
4
, do not affect interrupt operations. The interrupt generating signals from the interrupt mask circuit unit
6
are provided to the priority determining circuit unit
7
. The priority determining circuit unit
7
determines priorities of the interrupt signals, received in response to an interrupt priority instruction from the interrupt priority register
5
, and forwards the priority signal to the interrupt terminal at the CPU
1
. At the same time, record information on a source peripheral device
2
, which provides the interrupt signal to the CPU
1
, is stored at the interrupt status register
9
.
As an interrupt is generated, at step S
1
, the CPU
1
executes an instruction to stop running the present program and branch to a location where there is an interrupt service routine, for example, to location 18h. That is, 18h includes an instruction to branch to the interrupt service routine. At step S
2
, processing for other interrupts is disabled, because during execution of the service routine, execution of other interrupts is forbidden. At step S
3
, the system reads information from the interrupt status register
9
in the interrupt controller
3
. At step S
4
, the information is analysed to find the peripheral device that generated the interrupt. At step S
5
, an address of an actual service routine of the device is determined, and at step S
6
, the actual service routine is accessed and executed, to process the interrupt generated by the interrupt controller
3
.
However, as described above, the related art interrupt controller has various disadvantages. For example, the foregoing related art interrupt controller and method for controlling an interrupt have a slow response time. Upon entering into the interrupt service routing, the sequential steps of reading the interrupt status register to determine a peripheral device that generated the interrupt, and calculating an address to branch to for making the actual interrupt service, results in a prolonged response time from the generation of the interrupt to the response.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
SUMMARY OF THE INVENTION
An object of the present invention is to substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
Another object of the present invention is to provide a faster response time from the generation of an interrupt.
Another object of the present invention is to executes the actual interrupt service directly after sending an interrupt signal.
Another object of the present invention is to use an interrupt instruction register that stores a plurality of branch information regarding interrupts for the CPU prior to receipt of one of the corresponding interrupts from a corresponding plurality of peripheral devices.
The above objects of the present invention can be achieved, in a whole or in part, by an interrupt controller and method that includes an interrupt mask register that receives and stores an interrupt on/off instruction from a CPU. An interrupt priority register receives and stores an interrupt priority instruction from the CPU. An interrupt mask circuit unit selectively receives and forwards interrupt generating signals from peripheral devices, in response to an interrupt on/off instruction from the interrupt mask register. A priority determining circuit unit receives the interrupt generating signals from the interrupt mask circuit unit and determines priorities of the interrupt generating signals, in response to the interrupt priority instruction from an interrupt priority register, and forwards a priority signal to an interrupt terminal at the CPU.
An interrupt status register stores information of an interrupt signal from a source peripheral device, forwarded from the priority determining circuit unit, and provides a register selection signal corresponding to the information. An interrupt instruction register stores a branch instruction received from the CPU, and provides an interrupt instruction to the CPU in response to a register selection signal, that is received from the interrupt status register. A bus interface circuit unit transfers an address signal between the CPU and the interrupt controller. The interrupt controller also includes a buffer unit that buffers a data signal from the CPU to the interrupt controller.
To further achieve the above objects in a whole or in parts, there is provided an interrupt controller according to the present invention that includes an interrupt instruction unit that stores branch instruction data for processing an interrupt, a bus interface unit, and an interrupt instruction unit. Prior to an occurrence of the interrupt, the bus interface unit transfers the branch instruction data from a CPU to the interrupt instruction unit. After the occurrence of the interrup

Affiliated with

Also associated with

Rating

Interrupt controller does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Interrupt controller, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interrupt controller will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3140398