Electrical computers and digital data processing systems: input/ – Interrupt processing
Reexamination Certificate
1999-07-28
2003-03-25
Auve, Glenn A. (Department: 2181)
Electrical computers and digital data processing systems: input/
Interrupt processing
Reexamination Certificate
active
06539447
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a technique for supporting an interrupt managing function of an operating system (hereinafter referred to as “OS”) of an information processing device and, in particular, to an OS support system which can coexist with an OS having an interrupt managing function of a low realtime characteristic or performance so as to enhance a realtime performance for a given interrupt process. The OS having the interrupt managing function of the low realtime performance represents such an OS that requires a relatively long time after an occurrence of an interrupt request until the start of execution of a corresponding interrupt process. For instance, it represents such an OS that requires ten-odd microseconds after an occurrence of an interrupt request until starting the execution of a corresponding interrupt process while the interrupt process should be executed within several microseconds.
2. Description of the Invention
In general, recent OS's have an interrupt managing function so that when an interrupt request is produced from a CPU (processor unit), the OS determines an interrupt cause and manages the interrupt processing according to a result of the determination.
Specifically, addresses of an interrupt processing means, which executes an interrupt process and other processes, are first set in an interrupt vector area formed in a fixed memory or the like accessible by the CPU. The interrupt processing means represents a program for executing an interrupt process corresponding to an interrupt cause and a startup/execution means thereof.
The CPU issues an interrupt request to the OS by referring to a base address (an address to be first referred to) of the vector area. The OS holds operation environment information of the CPU, such as the contents of CPU registers, before the interrupt and transfers a control right on the interrupt request to the interrupt processing means. After executing a required interrupt process, the interrupt processing means returns the control right to the OS. The OS restores the operation environment information of the CPU before the interrupt so that the CPU can restart the processing from the state at the time of suspension.
On the other hand, there are available such OS's whose realtime performance of the interrupt managing function does not reach a standard required by an application. For instance, it is assumed that an application requires execution of an interrupt process within several microseconds after an occurrence of an interrupt request. In this case, if an OS requires ten-odd microseconds for executing the interrupt process, the required interrupt process corresponding to the interrupt request can not be accomplished.
As appreciated, it is possible to enhance the realtime performance by reconstructing the interrupt managing function of the OS. In this case, however, it is necessary to investigate in advance the contents of the interrupt managing function of the OS and carry out operations for reconstruction and test, thereby resulting in huge cost. In addition, once the OS is altered, the reconstructed function should be modified upon every version-up of the OS. Moreover, when the altered OS is used, the managing manner of the vector area should be modified so as to match with the interrupt managing manner adopted by the altered OS.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide an interrupt processing method which can enhance, without altering an OS, a realtime performance for an interrupt process in a device installing the OS.
It is another object of the present invention to provide an OS support system which can coexist with the OS so as to enhance the realtime performance for the interrupt process.
It is another object of the present invention to provide an information processing device having the OS and the OS support system.
It is another object of the present invention to provide a storage medium suitable for realizing the interrupt processing method using a general-purpose information processing device.
According to one aspect of the present invention, there is provided an interrupt processing method comprising the steps of providing in an information processing device an OS having an interrupt managing function and an OS support system for executing a given interrupt process which requires a high realtime performance; causing the OS support system to take an interrupt request produced in the information processing device earlier than the OS does and to judge whether the interrupt request corresponds to the given interrupt process; causing the OS support system to execute the given interrupt process when the interrupt request corresponds to the given interrupt process while transferring a control right on the interrupt request from the OS support system to the OS when the interrupt request does not correspond to the given interrupt process.
In the foregoing method, a time required by the OS support system after receipt of the interrupt request until starting execution of the given interrupt process is shorter than a time required by the OS after receipt of the interrupt request until starting execution of a corresponding interrupt process.
The OS and the OS support system may execute the interrupt processing independently of each other, or may execute the interrupt processing cooperatively with each other in a shared manner. In the latter case, a driver may be incorporated in the OS for exchanging relative to the OS support system, and the OS and the OS support system execute different interrupt processes in the same hardware in a shared manner via the driver. With this arrangement, the high-level interrupt processing corresponding to uses can be implemented while maintaining identity of the OS.
For enhancing generality, the OS support system may be installed in the information processing device after the OS is installed in the information processing device.
According to another aspect of the present invention, there is provided an OS support system which coexists with an OS having an interrupt processing function in an information processing device and is activated through initialization of the OS, the system comprising an interrupt recording section for recording contents of an interrupt process requiring a high realtime performance; an interrupt judging section for receiving an interrupt request earlier than the OS does when the interrupt request occurs in the information processing device, and judging whether the interrupt request corresponds to the interrupt process recorded in the interrupt recording section; and an interrupt executing section for executing the interrupt process when the interrupt request corresponds to the interrupt process, wherein the OS support system causes the OS to execute an interrupt process which is not recorded in the interrupt recording section.
It may be arranged that the OS support system coexists with the OS while maintaining identify of the OS, and implements interrupt processing independently of the OS. Alternatively, it may be arranged that a control driver is incorporated in the OS for realizing cooperation with the OS support system and that the OS support system implements interrupt processing cooperatively with the OS in a shared manner. In the latter case, it is easy to execute an interrupt process requiring a high realtime performance and an interrupt process not requiring it in a shared manner for the same control object.
According to another aspect of the present invention, there is provided an information processing device comprising a CPU issuing an interrupt request, an OS having an interrupt vector area and an OS support system having an extended interrupt vector area, wherein the CPU is capable of changing a base address of the interrupt vector area or the extended interrupt vector area to be referred to, wherein the interrupt vector area is set so that a control right is transferred to an interrupt process in the OS, and wherein the OS support system
Auve Glenn A.
Bachman & LaPointe
Chung-Trans X.
Elmic Systems, Inc.
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