Interrupt control on SMM

Details Interrupt control on SMM Interrupt control on SMM

1998-05-06

2000-03-14

Auve, Glenn A.

Electrical computers and digital data processing systems: input/

Interrupt processing

710104, G06F 946

Patent

active

060386320

ABSTRACT:
In an initialization operation of a system, an I/O trap SMI is issued to a CPU, and CPU state map information is stored in a predetermined area in an SM-RAM. When an interrupt control process occurs during the activation of an OS, the CPU state map information formed in the initialization operation is set in the CPU, and the CPU operation mode is changed to an original mode in which interrupts from various I/O devices are enabled. In the original mode of the CPU, parallel processing using an interrupt is executed. Initialization commands are sequentially issued to a plurality of devices such as a KBC, an HDD, and a display controller. The KBC, the HDD, and the display controller generate command completion interrupt signals upon completion of the command processes for their initialization operations. Next commands are sequentially issued to devices which have generated the command completion interrupt signals. A plurality of devices are initialized in accordance with the command completion interrupt signals from these devices.

REFERENCES:
patent: 5339437 (1994-08-01), Yuen
patent: 5671422 (1997-09-01), Datta
patent: 5764999 (1998-06-01), Wilcox et al.

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