Interrupt control device sending data to a processor at an...

Details Interrupt control device sending data to a processor at an... Interrupt control device sending data to a processor at an...

2008-01-22

2008-01-22

Rinehart, Mark H. (Department: 2111)

Electrical computers and digital data processing systems: input/

Interrupt processing

C710S058000, C710S059000

Reexamination Certificate

active

07321945

ABSTRACT:
An interrupt control device for issuing interrupts to a central processing unit (CPU) includes an object acquiring unit for acquiring data or resource(s) for use by the CPU and an interrupt issuing unit for issuing interrupts to the CPU. The interrupt issuing unit issues each interrupt to the CPU before the object acquiring unit actually acquires the data or the resource, but the interrupt indicates that the data or the resource is available. The interrupt control device further includes a use delay unit for delaying the use of the data or resource by the CPU unit until the object acquiring unit acquires the data or the resource if the CPU which has received the interrupt requests the use of the data or the resource before the object acquiring unit acquires the data or the resource. By adjusting the exact timing of the issuance of the interrupt according to the actual delays experienced by the CPU, the overall delays associated with interrupt handling are minimized.

REFERENCES:
patent: 5671365 (1997-09-01), Binford et al.
patent: 5881296 (1999-03-01), Williams et al.
patent: 6061305 (2000-05-01), Williams
patent: 6115776 (2000-09-01), Reid et al.
patent: 6167480 (2000-12-01), Williams et al.
patent: 6185639 (2001-02-01), Kailash et al.
patent: 6338111 (2002-01-01), Stevens
patent: 6397282 (2002-05-01), Hashimoto et al.
patent: 6629179 (2003-09-01), Bashford
patent: 6640274 (2003-10-01), Huffman et al.
patent: 6721878 (2004-04-01), Paul et al.
patent: 6754738 (2004-06-01), Brice et al.
patent: 2004/0236875 (2004-11-01), Jinzaki
patent: 10-275136 (1998-10-01), None
Constantinos Dovrolis, Brad Thayer, Parameswaran Ramanathan, “HIP: Hybrid Interrupt-Polling for the Network Interface”, 2001, ACM SIGOPS Operating Systems Review, ACM Press, vol. 35, Issue 4, pp. 50-60.
“Computer Dictionary”, 1994, Microsoft Press, Second Edition, p. 339.
Nakashima et al., “An Accurate and Efficient Simulation-based Analysis for Worst Case Interruption Delay”, Oct. 2006, ACM Press, Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems, pp. 2-12.
Van der Wijngaart et al., “The Effect of Interrupts on Software Pipeline Execution on Message-Passing Architectures”, Jan. 1996, ACM Press, Proceedings of the 10th international conference on Supercomputing, pp. 189-196.
Regehr et al., “Preventing Interrupt Overload”, Jun. 2005, ACM Press, Proceedings of the 2005 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems, pp. 50-58.
De Gloria et al., “A Self Timed Interrupt Controller: A Case Study in Asychronous Micro-Architecture Design”, Sep. 1994, IEEE, ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International, pp. 296-299.

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