Interrupt coalescing control scheme

Electrical computers and digital data processing systems: input/ – Interrupt processing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C710S262000, C710S263000, C710S266000, C710S268000

Reexamination Certificate

active

07987307

ABSTRACT:
In an embodiment, a method is provided. The method of this embodiment provides determining a flow context associated with a receive packet; and if the flow context complies with a dynamic interrupt moderation policy having one or more rules, generating an interrupt to process the receive packet substantially independently of an interrupt generated in accordance with an interrupt coalescing scheme (“coalesced interrupt”). Other embodiments are disclosed and/or claimed.

REFERENCES:
patent: 5708814 (1998-01-01), Short et al.
patent: 5764895 (1998-06-01), Chung
patent: 5881296 (1999-03-01), Williams et al.
patent: 5905913 (1999-05-01), Garrett et al.
patent: 5943479 (1999-08-01), Klein et al.
patent: 6085277 (2000-07-01), Nordstrom et al.
patent: 6115776 (2000-09-01), Reid et al.
patent: 6192440 (2001-02-01), Lowe et al.
patent: 6195725 (2001-02-01), Luhmann
patent: 6389526 (2002-05-01), Keller et al.
patent: 6574694 (2003-06-01), Chen et al.
patent: 6615305 (2003-09-01), Olesen et al.
patent: 6633941 (2003-10-01), Dunlap et al.
patent: 6718413 (2004-04-01), Wilson et al.
patent: 6760799 (2004-07-01), Dunlap et al.
patent: 7103693 (2006-09-01), Anand et al.
patent: 7124293 (2006-10-01), Mualem et al.
patent: 7159030 (2007-01-01), Elzur
patent: 7379453 (2008-05-01), DiMambro
patent: 7478186 (2009-01-01), Onufryk et al.
patent: 2003/0110281 (2003-06-01), Minnick et al.
patent: 2004/0125750 (2004-07-01), Katti et al.
patent: 2005/0228922 (2005-10-01), Tsao et al.
patent: 2006/0104303 (2006-05-01), Makineni et al.
patent: 2007/0043347 (2007-02-01), Solomita et al.
patent: 2007/0291778 (2007-12-01), Huang et al.
patent: 752799 (1997-01-01), None
patent: 04053333 (1992-02-01), None
patent: 04354222 (1992-12-01), None
patent: 05183581 (1993-07-01), None
patent: 2000261497 (2000-09-01), None
patent: 2001156851 (2001-06-01), None
patent: 2010244179 (2010-10-01), None
Miura et al., “RI2N/DRV: Multi-link ethernet for high-bandwidth and fault-tolerant network on PC clusters,” Parallel & Distributed Processing, 2009. IPDPS 2009. IEEE International Symposium on , pp. 1-7, May 23-29, 2009.
Regnier et al., “TCP onloading for data center servers,” Computer , vol. 37, No. 11, pp. 48-58, Nov. 2004.
Loeser et al., “Using Switched Ethernet for Hard Real-Time Communication,” Parallel Computing in Electrical Engineering, 2004. PARELEC 2004. International Conference on , pp. 349-353, Sep. 7-10, 2004.
Shen-Ming et al., “Design and implementation of the high speed TCP/IP Offload Engine,” Communications and Information Technologies, 2007. ISCIT '07. International Symposium on , pp. 574-579, Oct. 17-19, 2007.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Interrupt coalescing control scheme does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Interrupt coalescing control scheme, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interrupt coalescing control scheme will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2724482

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.