Interrupt capture and hold mechanism

Details Interrupt capture and hold mechanism Interrupt capture and hold mechanism

1998-01-16

2000-05-30

Sheikh, Ayaz R.

Electrical computers and digital data processing systems: input/

Interrupt processing

710261, 710262, 710266, 710267, G06F 946

Patent

active

060702184

ABSTRACT:
A processor is provided with an interrupt capture and hold mechanism. In one embodiment, a processor includes an instruction pipeline having stages for executing instructions. In the event of an exception, the instructions in the pipeline are flushed or aborted. This requires that each stage in the pipeline receive and respond to an exception-causing signal. An interrupt is an exception causing signal which may be provided by circuitry external to the processor. To ensure that such a signal is asserted long enough for each stage in the pipeline to receive and respond to it, all external hardware interrupts are routed through an interrupt capture and hold mechanism, thereby advantageously preventing the causation of an undefined processor state with little added complexity.

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Frantz et al., "The Texas Instruments TMS320C25 Digital Signal Microcomputer," IEEE Micro, No. 6, Dec. 1986, pp. 10-27.

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