Interrupt balancing for multi-core and power

Details Interrupt balancing for multi-core and power Interrupt balancing for multi-core and power

2011-06-14

2011-06-14

Stiglic, Ryan M (Department: 2111)

Electrical computers and digital data processing systems: input/

Interrupt processing

Multimode interrupt processing

C710S266000, C710S267000, C710S268000

Reexamination Certificate

active

07962679

ABSTRACT:
A method and apparatus for balancing power savings and performance in handling interrupts is herein described. When an amount of interrupt activity is above a threshold, a performance mode of interrupt handling is selected. During the performance mode, interrupts and/or interrupt sources are distributed among multiple physical sockets, i.e. multiple physical processors. However, if the interrupt activity is below a threshold for a number of periods, which denotes low interrupt activity, then a power save mode is selected. Here, interrupts and/or sources are primarily assigned to a single processor to allow other physical processors to save power. Furthermore, after interrupts are assigned to a physical processor, the interrupts may be further distributed among cache domains of the processor. In addition, high activity classes, interrupt sources, interrupts, or categories may be further assigned to specific processing elements for servicing.

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