Electrical computers and digital data processing systems: input/ – Interrupt processing
Reexamination Certificate
2001-03-02
2004-11-09
Dang, Khanh (Department: 2111)
Electrical computers and digital data processing systems: input/
Interrupt processing
C710S266000
Reexamination Certificate
active
06816935
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to input/output (I/O) buses, and more specifically, to interrupt reporting schemes for devices sharing such buses.
2. Description of the Relevant Art
With continuous advances in computer systems, manufacturers of peripheral devices have created a large number of new devices. Problems that arise from new devices often times drives the creation of new input/output (I/O) buses to overcome these problems. Examples of such I/O bus architectures include the Peripheral Component Interface (PCI) bus, Universal Serial Bus (USB), and the Advanced Graphics Port (AGP). Each of these bus architectures was developed to solve specific problems related to various types of peripherals that now utilize these buses.
Various problems must be solved in order to implement a new bus type. One such problem is the interfacing of the bus to a computer system. Each new bus type must include a hardware mechanism in order to allow it to communicate with a host computer system. Furthermore, communications protocols must be developed to allow a hardware interface to communicate with devices coupled to the peripheral bus. The hardware interface must also be configured to communicate with a bus interface in a host computer system, and must include mechanisms for reporting interrupt and status information of the various peripheral devices to the host computer.
With respect to communications protocols, several factors must be considered. In the case of a serial time-division bus which uses frames, the organization of the frames is an important factor. Frames may be structured to carry various types of commands and data, and must be able to allow a host computer system to determine control and status information for each peripheral device coupled to the bus. Interrupt reporting and handling is another factor that must be considered in organizing a frame structure for a time division bus. Furthermore, it may be necessary to organize a frame structure to carry large amounts of stream data between a peripheral device and a host computer system.
Interrupt and status reporting may be another function of a communications protocol for a serial time-division bus. Peripheral devices coupled to the bus may be capable of requesting an interrupt from a host computer system. In many such computer systems, the processor must then poll each device to determine the source of the interrupt. This may require a bus read by the processor, which may raise latency issues, since a processor typically operates at a much higher clock rate than a peripheral bus. Futhermore, peripheral devices may from time to time need to report a change of status (such as a change from an active to inactive mode) to a host computer system. Such reporting may also require a bus read by a processor, thus raise further latency issues.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by an interrupt and status reporting method and structure for a timeslot bus communications protocol. In one embodiment, a peripheral bus is a timeslot bus configured to transmit information across the bus in frames. Each frame may include at least one timeslot dedicated to reporting interrupt and status information to a host computer system. An interrupt request bit may be transmitted by a peripheral to a peripheral bus host controller, and may signal a request for an interrupt by a peripheral device. The requesting peripheral device may also transmit a cause code, which may include general information about the cause of the interrupt request, and a parameter field, which may include specific information about the cause of the interrupt request. Additionally, a peripheral device may be configured to use the interrupt and status reporting structure to request data to be transmitted to it from a host controller.
In one embodiment, the information interrupt and status information transmitted from a peripheral device to a host controller may be stored in registers of the host controller. This may allow a processor of a host computer system to determine the source of the interrupt request, as well as related information (the cause code and parameter fields) without being forced to conduct a bus read. Since many processors operate at a higher clock speed than a various peripheral buses, the ability to obtain information without performing a bus read may prevent latency issues that would otherwise arise due to the different clock speeds.
The interrupt and status reporting structure may also include one or more bits for requesting data from the host computer system. In one embodiment, bits are present for requesting data to be transmitted in one of two different data streams. The data transmitted in the streams may be any type of data used or processed by the peripheral (e.g. data to be transmitted onto a network by a network interface card).
Thus, in various embodiment, the interrupt and status reporting method and structure may allow for more efficient reporting of interrupt and status information to a host computer system. This may allow for more efficient handling of interrupts requested by peripherals coupled to a peripheral bus. Additionally, the interrupt and status reporting structure may allow a peripheral device to request data transmissions from a host computer system.
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Advanced Micro Devices , Inc.
Dang Khanh
Kivlin B. Noäl
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