Interrupt and message batching apparatus and method

Details Interrupt and message batching apparatus and method Interrupt and message batching apparatus and method

1997-10-15

2000-07-04

Shin, Christopher B.

Electrical computers and digital data processing systems: input/

Interrupt processing

Interrupt queuing

710 62, G06F 1300

Patent

active

060852771

ABSTRACT:
An interrupt and message batching apparatus and method reduces the number and frequency of processor interrupts and resulting context switches by grouping I/O completion events together with a single processor interrupt in a manner that balances I/O operation latency requirements with processor utilization requirements to optimize overall computer system performance. The invention sends a message from a processor complex to an I/O adapter on an I/O bus commanding an I/O device connected to the I/O adapter to perform a function. Upon completion of the commanded function, the message processor in the I/O adapter generates a message and sends it to the processor complex on the I/O bus. The message is enqueued in the message queue of the memory, a message count is updated, and processor complex interrupt is signalled if and when the message count exceeds a message pacing count. A signalling timer may also be programmed with a fast response time value if the message has a relatively high latency or with a slow response time value if the message has a relatively low latency. The signalling timer is started when the message is enqueued and the processor complex interrupt is then signalled when the message count exceeds the message pacing count or when the signalling timer has elapsed.

REFERENCES:
patent: 4783730 (1988-11-01), Fisher
patent: 5471618 (1995-11-01), Isfed
patent: 5507032 (1996-04-01), Kimura
patent: 5513368 (1996-04-01), Garcia, Jr. et al.
patent: 5535420 (1996-07-01), Kardach et al.
patent: 5708814 (1998-01-01), Short et al.
patent: 5761427 (1998-06-01), Shah et al.
patent: 5805929 (1998-09-01), Connolly et al.
patent: 5875343 (1999-02-01), Binford et al.
Inside the AS/400, Chapter 10, pp. 253-275, by Frank Soltis, Duke Press, Loveland, Colorado, 1996.
"PCI Local Bus Specification," Product Version, Revision 2.1, Jun. 1, 1995, pp. 1-282.

Affiliated with

Also associated with

Rating

Interrupt and message batching apparatus and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Interrupt and message batching apparatus and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interrupt and message batching apparatus and method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1496050