Interrupt and exception handling for multi-streaming digital...

Details Interrupt and exception handling for multi-streaming digital... Interrupt and exception handling for multi-streaming digital...

2011-03-01

2011-03-01

Donaghue, Larry (Department: 2454)

Electrical computers and digital processing systems: virtual mac

Task management or control

Process scheduling

C712S023000

Reexamination Certificate

active

07900207

ABSTRACT:
A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler logic. The logic detects and maps interrupts and exceptions to one or more specific streams. In some embodiments, one interrupt or exception may be mapped to two or more streams, and in others two or more interrupts or exceptions may be mapped to one stream. Mapping may be static and determined at processor design, programmable, with data stored and amendable, or conditional and dynamic, the interrupt logic executing an algorithm sensitive to variables to determine the mapping. Interrupts may be external interrupts generated by devices external to the processor software (internal) interrupts generated by active streams, or conditional, based on variables. After interrupts are acknowledged, streams to which interrupts or exceptions are mapped are vectored to appropriate service routines. In a synchronous method, no vectoring occurs until all streams to which an interrupt is mapped acknowledge the interrupt.

REFERENCES:
patent: 4197579 (1980-04-01), Otis, Jr. et al.
patent: 4200927 (1980-04-01), Hughes et al.
patent: 5142676 (1992-08-01), Fried et al.
patent: 5291586 (1994-03-01), Jen et al.
patent: 5309173 (1994-05-01), Izzi et al.
patent: 5321823 (1994-06-01), Grundmann et al.
patent: 5361337 (1994-11-01), Okin
patent: 5390307 (1995-02-01), Yoshida
patent: 5461722 (1995-10-01), Goto
patent: 5511210 (1996-04-01), Nishikawa et al.
patent: 5535365 (1996-07-01), Barriuso et al.
patent: 5542088 (1996-07-01), Jennings, Jr. et al.
patent: 5546593 (1996-08-01), Kimura et al.
patent: 5561776 (1996-10-01), Popescu et al.
patent: 5572704 (1996-11-01), Bratt et al.
patent: 5600837 (1997-02-01), Artieri
patent: 5604877 (1997-02-01), Hoyt et al.
patent: 5632025 (1997-05-01), Bratt et al.
patent: 5649144 (1997-07-01), Gostin et al.
patent: 5694572 (1997-12-01), Ryan
patent: 5701432 (1997-12-01), Wong et al.
patent: 5713038 (1998-01-01), Motomura
patent: 5737590 (1998-04-01), Hara
patent: 5745778 (1998-04-01), Alfieri
patent: 5748468 (1998-05-01), Notenboom et al.
patent: 5758142 (1998-05-01), McFarling et al.
patent: 5758195 (1998-05-01), Balmer
patent: 5784613 (1998-07-01), Tamirisa
patent: 5812811 (1998-09-01), Dubey et al.
patent: 5815733 (1998-09-01), Anderson et al.
patent: 5852726 (1998-12-01), Lin et al.
patent: 5860017 (1999-01-01), Sharangpani et al.
patent: 5867725 (1999-02-01), Fung et al.
patent: 5913049 (1999-06-01), Shiell et al.
patent: 5913054 (1999-06-01), Mallick et al.
patent: 5933627 (1999-08-01), Parady
patent: 5946711 (1999-08-01), Donnelly
patent: 5987492 (1999-11-01), Yue
patent: 6016542 (2000-01-01), Gottlieb et al.
patent: 6018759 (2000-01-01), Doing et al.
patent: 6029228 (2000-02-01), Cai et al.
patent: 6052708 (2000-04-01), Flynn et al.
patent: 6061710 (2000-05-01), Eickemeyer et al.
patent: 6076157 (2000-06-01), Borkenhagen et al.
patent: 6105127 (2000-08-01), Kimura et al.
patent: 6115802 (2000-09-01), Tock et al.
patent: 6119203 (2000-09-01), Snyder et al.
patent: 6192384 (2001-02-01), Dally et al.
patent: 6212544 (2001-04-01), Borkenhagen et al.
patent: 6260077 (2001-07-01), Rangarajan et al.
patent: 6260138 (2001-07-01), Harris
patent: 6266752 (2001-07-01), Witt et al.
patent: 6272624 (2001-08-01), Giacalone et al.
patent: 6292888 (2001-09-01), Nemirovsky et al.
patent: 6308261 (2001-10-01), Morris et al.
patent: 6356996 (2002-03-01), Adams
patent: 6389449 (2002-05-01), Nemirovsky et al.
patent: 6430593 (2002-08-01), Lindsley
patent: 6442675 (2002-08-01), Derrick et al.
patent: 6477562 (2002-11-01), Nemirovsky et al.
patent: 6487571 (2002-11-01), Voldman
patent: 6493749 (2002-12-01), Paxhia et al.
patent: 6502185 (2002-12-01), Keller et al.
patent: 6535905 (2003-03-01), Kalafatis et al.
patent: 6789100 (2004-09-01), Nemirovsky et al.
patent: 6792524 (2004-09-01), Peterson et al.
patent: 7020879 (2006-03-01), Nemirovsky et al.
patent: 7035997 (2006-04-01), Musoll et al.
patent: 7237093 (2007-06-01), Musoll et al.
patent: 7467385 (2008-12-01), Nemirovsky et al.
patent: 2002/0002607 (2002-01-01), Ludovici et al.
patent: 2002/0062435 (2002-05-01), Nemirovsky et al.
patent: 2003/0084269 (2003-05-01), Drysdale et al.
patent: 2005/0081214 (2005-04-01), Nemirovsky et al.
patent: 2007/0143580 (2007-06-01), Musoll et al.
patent: 2007/0294702 (2007-12-01), Melvin et al.
patent: 2008/0040577 (2008-02-01), Nemirovsky et al.
patent: 2009/0187739 (2009-07-01), Nemirovsky et al.
patent: 0764900 (1996-09-01), None
patent: 0806730 (1997-11-01), None
patent: 0827071 (1998-03-01), None
patent: 0953903 (1999-11-01), None
patent: 2321984 (1998-06-01), None
patent: 2103630 (1988-10-01), None
patent: 4335431 (1992-11-01), None
patent: 546379 (1993-02-01), None
patent: 09506752 (1997-06-01), None
patent: 1011301 (1998-01-01), None
patent: 10124316 (1998-05-01), None
patent: 10207717 (1998-08-01), None
patent: 63254530 (1998-10-01), None
patent: WO 94/27216 (1994-11-01), None
patent: WO 00/23891 (2000-04-01), None
patent: WO 00/36487 (2000-06-01), None
U.S. Appl. No. 09/592,103, filed Jun. 12, 2000, Melvin et al.
ARM Architecture Reference Manual. 1996. pp. 3-41, 3-42, 3-43, 3-67, and 3-68. Prentice Hall, NJ, US.
ESA/390 Principles of Operation. IBM Online Publications Center Reference No. SA22-7201-08. Table of Contents and paras. 7.5.31 and 7.5.70. IBM Corporation, Boulder, CO, US.
MC68020 32-Bit Microprocessor User's Manual, Third Edition, 1989, pp. 3-125, 3-126, and 3-127, Prentice Hall, New Jersey.
MC88110 Second Generation RISC Microprocessor RISC Microprocessor User's Manual. 1991. pp. 10-66, 10-67, and 10-17. Motorala, Inc.
“Parallel Long Move Instruction.” IBM Technical Disclosure Bulletin, IBM Corp., New York, US. vol. 33, No. 10A. Mar. 1, 1991. pp. 21-22, XP000109942 ISSN: 0018-8689.
The PowerPC Architecture: A Specification for a New Family of RISC Processors. 2ndEd. May 1994. pp. 70-72. Morgan Kaufmann. San Francisco, US.
Becker et al. “The PowerPC 601 Microprocessor.” IEEE Micro, Oct. 1993.
Bradford et al., “Efficient Synchronization for Multithreaded Processors.” Workshop on Multithreaded Execution, Architecture, and Compilation. Jan.-Feb. 1998. pp. 1-4.
Cui et al. “Parallel Replacement Mechanism for MultiThread.” Advances in Parallel and Distriuted Computing. 1997. Proceedings, IEEE, Mar. 21, 1977, pp. 338-344.
Diefendorff, Keith et al. “Organization of the Motorola 88110 Superscalar RISC Microprocessor.” IEEE Journal of Microelectronics. Apr. 1992. pp. 40-63. vol. 12, No. 2. IEEE. New York, NY, US.
Diefendorff, Keith. “jalapeño Powers Cyrix's M3.” Microprocessor Report. Nov. 16, 1998. vol. 12, No. 15.
Diefendorff, Keith. “WinChip 4 Thumbs Nose At ILP.” Microprocessor Report. Dec. 7, 1998. vo. 12, No. 16.
Diefendorff, Keith. “Compaq Chooses SMT for Alpha.” Microprocessor Report. Dec. 6, 1999.
Diefendorff, Keith et al. “AltiVec Extension to PowerPC Accelerates Media Processing.” IEEE Journal of Microelectronics. vol. 20, No. 2 (2000). pp. 85-95.
Donaldson et al. “DISC: Dynamic Instruction Stream Computer, An Evaluation of Performance.” 26thHawaii Conference on Systems Sciences. vol. 1. 1993. pp. 448-456.
Eggers et al. “Simultaneous Multithreading: A Platform for Next-Generation Processors.” IEEE Micro. Sep./Oct. 1997.
Fiske et al. Thread Prioritization: A Thread Scheduling Mechanism for Multiple-Context Parallel Processors. Proceedings of the First IEEE Symposium on High-Performance Computer Architecture. Jan. 1995. pp. 210-221. Raleigh, NC, US.
Grunewald et al. “Towards Extremely Fast Context Switching in a Block Multithreaded Processor.” Proceedings of EUROMICRO 22. pp. 592-599.
Grunewald et al. “Confidence Estimation for Speculation Control.” Computer Architecture. 1998. Proceedings. The 25thAnnual International Symposium on Barcelona, Spain. Jun. 27, 1998-Jul. 1, 1998. Los Alamitos, CA. U

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