Electrical computers and digital data processing systems: input/ – Interrupt processing
Reexamination Certificate
1999-04-28
2003-12-02
Marcelo, Melvin (Department: 2663)
Electrical computers and digital data processing systems: input/
Interrupt processing
C710S261000
Reexamination Certificate
active
06658514
ABSTRACT:
The invention relates to a microcomputer as well as a computer system and methods of operating such.
BACKGROUND OF THE INVENTION
Microcomputers may include on an integrated circuit chip a CPU together with other modules which need to intercommunicate. The communications between devices on the chip may include interrupt signals and control commands sent between devices which are interconnected on the chip.
It is an object of the present invention to provide an improved system for distributing interrupt and control signals between devices in a microcomputer or computer system.
SUMMARY OF THE INVENTION
The invention provides a computer system comprising an integrated circuit device with an address and data path distributing addressed packets between a source and destination and interconnecting a plurality of on-chip devices including at least one CPU with at least one different module, said CPU and said module each having circuitry to generate event request packets of two different types for distribution on said address and data path, each packet having a destination address, one type being a control command packet to which the destination device must respond on receipt and the other type being an interrupt request with a priority indicator so that the destination device may selectively respond depending on the priority detected.
Preferably said CPU includes packet generating circuitry responsive to receipt of an event request packet to generate an addressed response bit packet for distribution on said address and data path.
Preferably said different module includes packet generating circuitry responsive to receipt of a request packet to generate an addressed response bit packet for distribution on said address and data path.
Preferably said packet generating circuitry includes means to indicate the address of the destination for the packet as well as the address of the source of the packet.
The system may include an on chip memory interface and said packet generating circuitry is operable to generate memory access packets.
Preferably said CPU includes comparator circuitry for comparing priorities of event request packets received with the priority of any current CPU activity.
Preferably the packet generating circuitry of each device includes means to provide in the packet a number identifier for identifying a request packet together with circuitry for including the packet number identifier in any corresponding response packet whereby response packets may be matched to request packets.
Preferably a plurality of modules are provided on chip each having packet generating circuitry for generating event request packets, at least one module being arranged to generate event packets in the form of prioritised interrupt requests and at least another module being arranged to generate event request packets in the form of control packets providing control commands for the CPU.
The invention includes a method of operating a computer system comprising an integrated circuit device with an address and data path interconnecting a plurality of on chip devices including at least one CPU with at least one different module, said method comprising generating event request packets of two different types for distribution on said address and data path, each packet having a destination address, one type being a control command packet to which the destination device responds on receipt and the other type being an interrupt request packet with a priority indicator whereby the destination device selectively responds depending on the priority detect.
Preferably each event request packet includes an indicator of the source of the packet as well as an indicator of the destination of the packet.
Preferably the packet generating circuitry uses the source address included in each request packet to provide a destination address in a response packet.
Preferably each request packet includes a number identifier which is used at each destination to form part of the response packet whereby response packets are matched to request packets.
Preferably said event request packets are distributed in bit parallel format on said address and data path.
The packets are preferably each multi byte long.
REFERENCES:
patent: 4268904 (1981-05-01), Suzuki et al.
patent: 4839800 (1989-06-01), Barlow et al.
patent: 5060139 (1991-10-01), Theus
patent: 5067041 (1991-11-01), Cooke et al.
patent: 5265215 (1993-11-01), Fukuda et al.
patent: 5274767 (1993-12-01), Maskovyak
patent: 5283904 (1994-02-01), Carson et al.
patent: 5440698 (1995-08-01), Sindhu et al.
patent: 5495615 (1996-02-01), Nizar et al.
patent: 5689713 (1997-11-01), Normoyle et al.
patent: 5978870 (1999-11-01), Warren
patent: 6061757 (2000-05-01), Arimilli et al.
patent: 6170025 (2001-01-01), Drottar et al.
patent: 6295573 (2001-09-01), Bailey et al.
patent: 6301625 (2001-10-01), McDonald et al.
patent: 6389498 (2002-05-01), Edwards et al.
patent: 6397325 (2002-05-01), Jones et al.
patent: 6415344 (2002-07-01), Jones et al.
patent: 0 644 489 (1995-03-01), None
patent: WO 95/16965 (1995-06-01), None
Prohofsky, Thomas. “High Speed Data Bus Macro Instruction Set Architecture”. Aerospace and Electronics Conference, 1991. IEEE. pp. 192-196.*
Baker et al. “A Priority Event Monitor for an Interrupt Driven Microprocessor”. IEEE Proceedings of Southeastcon 1991. pp. 905-906.
Jones Andrew Michael
May Michael David
Carlson David V.
Ferris Derrick W
Jorgenson Lisa K.
Marcelo Melvin
SEED IP Law Group PLLC
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