Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2000-04-28
2003-03-11
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S112000, C438S121000, C438S123000, C438S124000, C438S125000, C257S678000, C257S687000
Reexamination Certificate
active
06531335
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to interposers for use in chip-scale packages (CSPs), including ball grid array (BGA) packages. Particularly, the present invention relates to interposers that include upwardly protruding dams configured to laterally confine encapsulant material over a specified area of the interposer. The invention also relates to semiconductor device packages including the interposers and to methods of fabricating the upwardly protruding dams, the interposers, and assemblies including the interposers.
2. Background of Related Art
Semiconductor Device Packages
Semiconductor devices, such as memory devices and processors, are generally fabricated in very large numbers. Typically, several semiconductor devices are fabricated on a wafer or other large scale substrate that includes a layer of semiconductor material (e.g., silicon, gallium arsenide, or indium phosphide). The semiconductor devices are then singulated, or diced, from the wafer or other large scale substrate to provide semiconductor “chips” or dice.
Conventionally, semiconductor dice have been packaged for protection and to facilitate the formation of electrical connections to the small bond pads thereof. Conventional semiconductor device packages typically include an assembly of a semiconductor die and a higher level substrate board (e.g., a circuit board) or leads. Bond pads of the semiconductor die are electrically connected (e.g., by wire bonds or otherwise) to contact pads of a higher level substrate or to leads. The assembly may then be packaged. For example, assemblies that include a semiconductor die with leads connected to the bond pads thereof are typically packaged by use of transfer molding techniques to secure the leads in place and to protect the active surface of the semiconductor die and the wire bonds or other intermediate conductive elements. Assemblies including a semiconductor die and a higher level substrate may be packaged by injection molding techniques or with a glob-top type encapsulant, both of which protect the active surface of the semiconductor die and the wire bonds or other intermediate conductive elements.
Due to the ever-decreasing sizes of state of the art electronic devices, conventional semiconductor device packages are relatively bulky. As a result, alternative semiconductor device packaging configurations have been developed to reduce the amount of area, or “real estate”, on circuit boards consumed by semiconductor device packages.
Among these state of the art semiconductor device packages are the so-called chip-scale packages, the areas of which are substantially the same as or only slightly larger than the areas of the semiconductor dice thereof. Chip-scale packages may include a semiconductor die and an interposer superimposed over the semiconductor die. The bond pads of the semiconductor die are electrically connected to contact pads of the interposer, which are in turn electrically connected to a circuit board or other carrier substrate through traces extending to other contact elements that mate with terminals on the circuit board or other carrier substrate.
An exemplary ball grid array type chip-scale package
201
is illustrated in FIG.
1
. Package
201
includes a semiconductor die
202
and an interposer
206
positioned over an active surface
203
of semiconductor die
202
. Interposer
206
is secured to semiconductor die
202
with a layer
215
of adhesive material. A quantity of underfill material
216
is introduced between semiconductor die
202
and interposer
206
to fill any remaining open areas therebetween.
Interposer
206
includes a slot
207
formed therethrough. Bond pads
204
on an active surface
203
of semiconductor die
202
are exposed through slot
207
. Bond pads
204
are connected by way of wire bonds
205
or other intermediate conductive elements to corresponding first contact pads
208
on interposer
206
. As illustrated, wire bonds
205
extend through slot
207
. Each first contact pad
208
communicates with a corresponding second contact pad
209
on interposer
206
by way of a conductive trace
210
carried by interposer
206
. Second contact pads
209
may be arranged so as to reroute the output locations of bond pads
204
. Thus, the locations of second contact pads
209
may also impart interposer
206
with a desired footprint, and particularly one which corresponds to the arrangement of terminal pads on a carrier substrate (not shown) to which package
201
is to be connected. Bond pads
204
, wire bonds
205
, and first contact pads
208
are each protected by a quantity of an encapsulant material
211
, such as a glob-top type encapsulant.
Package
201
is electrically connected to a carrier substrate by way of conductive structures
213
, such as solder balls, connected to second contact pads
209
and corresponding contact pads of the carrier substrate. Package
201
is configured to be connected to a carrier substrate in an inverted, or flip-chip, fashion, which conserves real estate on the carrier substrate. It is also known in the art to connect a chip-scale package to a carrier substrate by way of wire bonds or other conductive elements. Such assemblies, packages and interposers are disclosed, for example, in U.S. Pat. No. 5,719,440, issued to Walter L. Moden and assigned to the assignee of the invention disclosed and claimed herein.
The introduction of underfill materials between a semiconductor die and an interposer secured thereto is somewhat undesirable since an additional assembly step is required. Moreover, as conventional underfill materials flow into the spaces between a semiconductor die and an interposer, voids or bubbles may form and remain therein.
In addition, the use of glob-top type encapsulants to protect the bond pads and intermediate conductive elements of such chip-scale packages is somewhat undesirable since glob-top encapsulants may flow laterally over the second contact pads or conductive structures protruding therefrom. While more viscous encapsulant materials may be used, because viscous glob-top encapsulants typically cure with a convex surface, the amount of encapsulant needed to adequately protect the bond wires or other intermediate conductive elements between the bond pads and first contact pads may result in a glob-top that protrudes an undesirable distance from the interposer, which may require the removal of some of the convex portion of the glob-top or the use of undesirably long conductive elements between the second contact pads of the interposer and the contact pads of the carrier substrate.
U.S. Pat. No. 5,714,800, issued to Patrick F. Thompson, discloses an interposer with a stepped outer periphery. The first contact pads are located on the lower, peripheral portion of the interposer, while the second contact pads are positioned on the higher, central region of the interposer. The vertical wall between the lower and higher regions of the interposer prevents liquid encapsulant material from flowing laterally beyond the lower portion of the interposer and thus prevents the liquid encapsulant material from flowing onto the second contact pads. As the lower, peripheral portion of the interposer must have a sufficient thickness and rigidity to support the first contact pads thereon and since the difference in height between the peripheral and central regions of the interposer should be sufficient to facilitate complete encapsulation of an intermediate conductive element, such as a bond wire, that is connected to and raised somewhat above a first contact pad, the stepped interposer is relatively thick and undesirably adds to the overall thickness of a semiconductor device package of which it is a part. Moreover, fabrication of the stepped interposer requires additional machining or alignment of layers to create a stepped periphery. In addition, when an interposer with a stepped periphery is used, since the intermediate conductive elements and bond pads are located near the periphery of the semiconductor die-in
Lee Granvill D
Smith Matthew
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