Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2003-03-14
2004-11-16
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S777000, C257S773000, C257S786000
Reexamination Certificate
active
06819001
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to the field of electronic interconnect systems, and more particularly, to an interposer and interposer package for facilitating electrical connection to, for example, an unpackaged integrated circuit device.
Today, integrated circuit devices can be fabricated with features as small as 0.1 microns, with input/output pads as small as 0.2 micron pitch, or less. Input/output pads for these devices are typically configured according to minimum interconnect features, i.e., input/output pad pitch is conventionally determined by an interconnect pitch and/or configuration capability, rather than a device or wafer pitch capability. The current minimum feature for flexible circuit interconnect is 10 microns and for flexible printed circuit board (PCB) is 50 microns. Accordingly, the existing interconnect systems used to connect device input/output to “system” input/output lag the theoretical maximum density of integrated circuits by 100× (for flexible interconnect) and by 500× (for PCB). Although alternative high density, fine pitch interconnect systems are contemplated, for example, carbon nanotubes, there currently exists an impediment or density barrier to interconnecting high density input/output devices to “systems”. This impediment results from functional performance, capability, and cost limitations of existing interconnect systems.
In order to maintain small package footprints and volumes for high density input/output (I/O) devices, area array configurations are often utilized. Area arrays provide enhanced input/output contacts for a given footprint or area, i.e., have high input/output density. This is especially true when the entire surface area is used for the area array input/output. However, because of circuit routing capabilities of both flexible circuits and PCB structures, it is often impossible, not feasible, and/or too expensive to construct device interconnect systems that can escape (i.e., route to another device, component, subsystem, etc.) such high density device I/O. Accordingly, device I/O quantity and configurations are again limited by interconnect system capability and density. Furthermore, even if not limited, high density interconnect systems are often incompatible with commonly used terminations for interconnection, for example, high density input/output sockets, clamps, etc.
SUMMARY OF THE INVENTION
The present invention provides, in one aspect, a structure comprising an interposer having a substrate formed of a semiconductor material, with first input/output contacts disposed over a first main surface thereof and second input/output contacts disposed over a second main surface thereof. The second input/output contacts are electrically connected to the first input/output contacts. The first input/output contacts are for attachment to input/output pads of a device to which the interposer is to be attached. The second input/output contacts disposed over the second main surface of the interposer's substrate facilitate coupling of the interposer to contacts of a component to which the interposer is also to be attached.
In another aspect, a structure is provided which includes an integrated circuit device having a substrate with input/output pads disposed over a surface thereof. The structure further includes an interposer which has a substrate formed of a semiconductor material, and has first input/output contacts disposed over a first main surface thereof and second input/output contacts disposed over a second main surface thereof. The second input/output contacts are electrically connected to the first input/output contacts. The first input/output contacts disposed over the first main surface of the substrate are electrically attached to the input/output pads of the integrated circuit device, and the second input/output contacts disposed over the second main surface facilitate coupling to contacts of a component to which the interposer can also be attached.
Methods of fabricating and connecting the above-summarized structures are also described and claimed herein. Further, other embodiments and aspects of the invention are described in detail and claimed herein.
REFERENCES:
patent: 3982268 (1976-09-01), Anthony et al.
patent: 5258648 (1993-11-01), Lin
patent: 6496370 (2002-12-01), Geusic et al.
Burdick, W. E., “Electronic Array and Methods for Fabricating Same”, pending U.S. patent application Ser. No. 10/313,078, filing date Dec. 6, 2002.
Burdick, Jr. William E.
Rose James W.
General Electric Company
Heslin Rothenberg Farley & & Mesiti P.C.
Prenty Mark V.
Radigan, Esq. Kevin P.
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