Interposer for mounting semiconductor dice on substrates

Details Interposer for mounting semiconductor dice on substrates Interposer for mounting semiconductor dice on substrates

1999-07-06

2001-10-16

Wong, Don (Department: 2821)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

C257S712000

Reexamination Certificate

active

06303992

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuit (IC) components, such as semiconductor dice, and more particularly to interposers for mounting semiconductor dice on substrates.
2. Disclosure Information
In conventional flip-chip mounting processes, a semiconductor IC die
50
(see
FIG. 1A
) is typically “bumped”, a process wherein thick metal layers (e.g., 25-100 microns) of gold or solder
24
are metallurgically bonded to the IC die's aluminum bond pads
54
. The bumped IC die is then flipped “upside down” with the bumps
24
facing downward against mating mounting pads
72
on a substrate
70
(e.g., a printed circuit board), whereupon solder reflow (for solder bumps) or diffusion bonding (for gold bumps) is used to bond the bumps with their respective substrate mounting pads, as illustrated in FIG.
1
B.
Because IC dies have traditionally been wire-bonded to leadframes and then encased in polymer or ceramic packages (as in DIPs, QFPs, etc.), the bond pads on an IC die are typically arranged about the periphery of the die's bonding surface (i.e., near the outer edge or perimeter of the die). This presents no problem for using flip-chip bonding so long as the die size is large, and/or the number of bond pads is low (thereby permitting the use of large pads); however, as the die size shrinks and/or the number of bond pads increases, the bond pads must be made smaller and/or more closely spaced (i.e., finer pitched), which makes registration and bonding of the bonding pads to the mounting pads much more difficult.
One way of addressing this problem has been to distribute the bond pads
24
across most of the entire face of the bonding surface (FIG.
2
), rather than limiting the bond pads to the conventional perimeter locations (FIG.
1
A). However, when the bond pads are brought inward from their typical perimeter locations toward the center of the bonding surface, they lie atop the transistors and other delicate solid state devices
52
located thereat, separated only by a thin passivation layer
56
. This presents a problem because the heat and/or pressure required to melt or diffuse the bumps
24
(in order to form metallurgical bonds between the bond pads and mounting pads) often damages the adjacent/underlying transistors and IC devices
56
. This problem has therefore limited flip-chip bonding, practically speaking, to the use of relatively low-temperature, low-pressure solder reflow processing with perimeter-only bond pad locations; but, as mentioned above, this places serious limits on the number of bond pads that can be used.
It would be desirable, therefore, to provide a way of enabling the use of a higher number of bond pads, without the aforementioned potential of damaging the delicate transistors and other IC devices.
SUMMARY OF THE INVENTION
The present invention overcomes the disadvantages of the prior art approaches by providing an interposer which enables connection of a semiconductor die to a substrate with the use of a high number (and/or larger sizes) of bond pads, without the aforementioned drawbacks. This interposer comprises: an interposer body made of a dielectric material and having a contact surface and an opposed bonding surface; a plurality of contact pads arranged about the periphery of the contact surface; a plurality of bonding pads arranged across generally the entire area of the bonding surface; and a plurality of electrically conductive conduits disposed generally within the interposer body, such that each conduit connects a respective one of the contact pads with a respective one of the bonding pads. The interposer may also include: a sealed cooling channel defined within the interposer body; a fluid medium generally filling the cooling channel; and a piezoelectric element attached to the interposer body such that the piezoelectric element communicates with the cooling channel and the fluid medium, the piezoelectric element being operatively coupled to at least two of the electrically conductive conduits.
It is an object and advantage that the interposer of the present invention enables the use of a higher number of bond pads, and/or larger bond pads, than would be provided using prior art approaches.
Another advantage is that the present invention enables the use of such larger and/or higher number of bond pads while greatly reducing the potential for damaging the delicate transistors and other IC devices of the semiconductor die.
Yet another advantage is that the piezoelectric element, cooling channels, and fluid medium cooperate to provide improved cooling for the attached semiconductor die.
These and other advantages, features and objects of the invention will become apparent from the drawings, detailed description and claims which follow.


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