Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1995-10-27
1998-03-31
Chin, Stephen
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
377 24, 364561, 364723, G01B 700
Patent
active
057346887
ABSTRACT:
Signals S.sub.j and S.sub.j-1 that are deviate from each other by a phase value of 2 .pi./M are generated by combining two sinusoidal detection signals. A reference signal .DELTA.S is generated which represents a difference between the signals S.sub.j and S.sub.j-1. An up-pulse or a down-pulse is generated every time the signal S.sub.j or S.sub.j-1 varies by .DELTA.S
. An n-ary reversible ring counter outputs a first count value and a carry or borrow pulse by counting the up-pulse and the down-pulse, and the first count value is used to control the operation of generating the up-pulse or down-pulse. An M-ary reversible ring counter outputs a second count value by counting the carry pulse or the borrow pulse, and the second count value is used to control the operation of generating the signals S.sub.j and S.sub.j-1.
REFERENCES:
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patent: 5218295 (1993-06-01), Nakazato et al.
patent: 5452425 (1995-09-01), Childers et al.
Okamoto Kiyokazu
Teraguchi Mikiya
Chin Stephen
Deppe Betsy L.
Mitutoyo Corporation
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