Internally ballasted silicon germanium transistor

Details Internally ballasted silicon germanium transistor Internally ballasted silicon germanium transistor

2001-03-19

2002-09-24

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Including semiconductor material other than silicon or...

Containing germanium, ge

C257S361000, C257S362000, C257S580000, C257S582000

Reexamination Certificate

active

06455919

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of bipolar transistors; more specifically, it relates to an internally ballasted silicon germanium bipolar transistor and the method of fabricating an internally ballasted silicon germanium bipolar transistor.
BACKGROUND OF THE INVENTION
Integrated circuits routinely include on-die circuits for electrostatic discharge (ESD). ESD phenomenon causes a high voltage and/or current to be impressed across the terminals of a device. Both voltage and current spikes may occur. These spikes, usually of very short duration, can break down the isolation or diffusions in various portions of individual semiconductor devices, thus rending the entire device completely or partially inoperable.
There are three models in use to describe ESD, the human body model, the 400-volt machine model and the charge device model. In the human body model a 4 KV pulse is assumed with a maximum current of 2.6 amperes with a 150 ns event time. In the 400-volt machine model, a maximum of 7 amperes is assumed with a 10 ns event time. In the charge device model, voltages as high as one KV and currents of 9 to 10 amperes with 0.25 ns event times are assumed. In general, ESD events occur at frequencies lower than five GHz.
Capacitive loading becomes a major concern for chips running at high frequencies, i.e. greater than one GHz, as the capacitive loading of conventional ESD devices has an adverse effect on device performance. The total capacitance looking into a device is given by:
C
TOT
=C
CKT
+C
ESD
Wherein:
C
TOT
=the capacitance looking into the die from an I/O pad;
C
CKT
=capacitance of the circuit being protected; and
C
ESD
=ESD device capacitance.
High-frequency circuits are designed with low capacitance, C
CKT
, but ESD circuits and devices have relatively high capacitance's. C
TOT
can become driven by C
ESD
and the chip fails to perform. One problem in fabricating low capacitance high frequency ESD devices and circuits is the maximum value of capacitance that can be tolerated. For example, at 1 GHz a capacitance of 1 pF is acceptable, but at 10 GHz, the capacitance must be in the order of 0.1 pF, which is difficult to achieve, and for 100 GHz the capacitance would need to be around 0.01 pF, very difficult (if even possible) to achieve with conventional ESD protection circuits.
A major use of silicon-germanium (SiGe) is in high-frequency circuits. SiGe bipolar transistors comprise a base comprised of a SiGe polysilicon region surrounding a SiGe epitaxial silicon region, the base region being located between a collector structure (normally a N+ pedestal integral to and raised above a subcollector) and an N+ polysilicon emitter. It would be particularly desirable to be able to fabricate ESD resistant SiGe devices for use in either high-frequency ESD protect circuits or for high-frequency driver/receiver (D/R) circuits.
SUMMARY OF THE INVENTION
A first aspect of the present invention is a bipolar transistor, comprising: a silicon substrate; a collector formed in the semiconductor substrate; a base formed over the collector, the base having an intrinsic base region and an extrinsic base region, the extrinsic base region forming an internal resistor; an emitter formed over the intrinsic base region; and a dielectric layer formed between the extrinsic base region and the collector, the extrinsic base region, the dielectric layer and the collector forming an internal capacitor.
A second aspect of the present invention is a bipolar transistor, comprising: a silicon substrate; a collector formed in the semiconductor substrate; a base formed over the collector, the base having an intrinsic base region and an extrinsic base region, the extrinsic base region forming an internal resistor between the base and a base contact; an emitter formed over the intrinsic base region; and a dielectric layer formed between the extrinsic base region and the collector, the extrinsic base region, the dielectric layer and the collector forming an internal capacitor between the base and a collector contact.
A third aspect of the present invention is a bipolar transistor, comprising: a silicon substrate, a sub-collector formed in the silicon substrate between a lower portion and an upper portion of the silicon substrate; a collector formed in the upper portion of the silicon substrate and over a portion of the subcollector, the collector contacting the subcollector and extending to a top surface of the silicon substrate; a base formed over the sub-collector, the base having an intrinsic base region and an extrinsic base region, the extrinsic base region forming an internal resistor; an emitter formed over the intrinsic base region; and a dielectric layer formed between the extrinsic base region and the upper portion of the silicon substrate. the extrinsic base region, the dielectric layer and the upper portion of the silicon substrate forming an internal capacitor.
A fourth aspect of Fe present invention is a method of fabricating a bipolar transistor, comprising: providing a silicon substrate; forming a sub-collector in the silicon substrate between a lower portion and an upper portion of the silicon substrate; forming a collector in the upper portion of the silicon substrate and over a portion of the subcollector, the collector contacting the subcollector and extending to a top surface of the silicon substrate; forming a first dielectric layer on a top surface of the silicon substrate; forming a base layer on top of the first dielectric layer and forming an opening in the first dielectric layer, the opening aligned over the collector; the base layer having an intrinsic base region aligned over the collector and a surrounding extrinsic base region; the extrinsic base region forming an internal resistor between an extrinsic base contact and the upper portion of the silicon substrate, and the extrinsic base region, the first dielectric layer and the upper portion of the silicon substrate forming an internal capacitor; forming a second dielectric layer; and forming an emitter layer on top of second dielectric layer and in an opening formed in the second dielectric layer, the opening aligned over the intrinsic base region.


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