Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2007-11-27
2007-11-27
Zarabian, Amir (Department: 2827)
Static information storage and retrieval
Read/write circuit
Testing
C365S189030, C365S189050
Reexamination Certificate
active
11225652
ABSTRACT:
Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the internal symmetry of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the asymmetric operation, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.
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Devgan Anirudh
Joshi Rajiv V.
Ye Qiuyi
Graham Kretelia
Harris Andrew M.
Mitch Harris Atty at Law, LLC
Salys Casimer K.
Zarabian Amir
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