Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2002-12-31
2004-08-10
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
Reexamination Certificate
active
06774712
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit for generating a voltage source in a semiconductor memory device.
2. Prior Art of the Invention
A rapid development in an electronic/communication industry brings about an appearance of handheld terminals having a multimedia function or an improved multimedia function. For instances, a handheld phone employing a code division multiple access-2000 system, a post PC, a handheld PC and a personal digital assistant (PDA) etc. have a DRAM built-in capable of processing a large capacity according to an increased requirement concerning a function of multimedia. Such handheld terminals have a supply of an operating voltage source from a battery, thus a battery saving is being on the rise as an important issue. Further, according that a size of such handheld terminals is getting miniaturized more and more, it is a tendency that a size and a capacity of the battery built-in are getting miniaturized. Therefore, a technique for saving electric power is being improved gradually. Accordingly, a work-use memory used in utilizing the handheld terminal, for example, a DRAM requires a high-speed/low consumption electric power and a large capacity. One of the most importance elements in using the DRAM in the handheld terminal is how to minimize current consumption of a DRAM.
To minimize the power consumption in a semiconductor memory device, an internal voltage source generating circuit is used for converting a voltage source supplied from the outside and for providing it to an internal circuit of a chip. In such an internal voltage source generating circuit and according to its construction, a level of external voltage source supplied from the outside of the chip is utilized so as to generate a reference voltage (“Vref”). Vref is then utilized to generate the internal voltage source (“IVC”). The IVC has a level necessary for respective circuits of the chip inside; for instances, peripheral circuits of a memory device and a memory array, etc. Such an IVC generating circuit is also called an Internal Voltage down Converter. An IVC generating circuit is useful in supplying a constant voltage source, changed from an external voltage source based on a wide range, to the inside of the chip. An example of such technique is described in detail in “Internal Voltage Source Generating Circuit and Semiconductor Memory Device therefore” (Hereinafter, “the Prior Patent”) which was filed, and was registered on Jun. 28, 2000 by the present Applicant.
The Prior Patent provides an internal voltage source generating circuit for supplying a power source to a data output buffer, requiring a voltage source generating circuit in the normal operating mode. Support of other operating modes may be required. For example, support for an operation of a Deep Power Down Mode (“DPD”) mode standardized in Joint Electron Device Engineering Council (“JEDEC”), to minimize power consumption in a semiconductor memory device. As is well-known in the art, the DPD mode minimizes a level of voltage source supplied to respective circuits provided within the DRAM, so as to become about 1 &mgr;A and below in power consumption when a system having a mounting of a memory does not use the DRAM. In other words, in this mode, there is no need to continuously maintain data stored in the DRAM.
A reference voltage generating circuit used in another semiconductor memory device was disclosed in U.S. Pat. No. 6,275,100 (hereinafter, “the Second Prior Patent”), patented by the present Applicant. The reference voltage generator disclosed in the second Prior Patent had at least one switch for switching a power source supply path between an input terminal of an external voltage source (“EVC”) and a power source input terminal of the reference voltage generator in response to a standby signal, provided from the outside of the semiconductor memory device. In such second Prior Patent, an operation of the DPD mode was not supported, since the EVC supplied to the reference voltage generator of a chip, from the outside of the chip, was completely cut off.
SUMMARY OF THE INVENTION
The present invention resolves the shortcomings of the prior art by implementing an internal voltage source generating circuit, which is operable to convert the voltage of an external voltage source to at least a first and a second voltage level. These levels are normally exclusive to one another and are meant to operate a semiconductor memory device which is capable of at least a first and second operating mode. In one exemplary embodiment, the at least first and second operating modes will respectfully coincide with the at least first and second voltage levels. Thus, the voltage level will depend on the operating mode of the semiconductor memory device. Other embodiments will be designed such that the first voltage level is a “normal” operating voltage level for the semiconductor memory device and the second voltage level is one that will support the Deep Power Down mode.
REFERENCES:
patent: 5689469 (1997-11-01), Asaka et al.
patent: 6081459 (2000-06-01), Kim
patent: 6084386 (2000-07-01), Takahashi et al.
patent: 6097113 (2000-08-01), Teraoka et al.
patent: 6275100 (2001-08-01), Park et al.
Chun Ki-Chul
Hong Sang-Pyo
Rhee Sang-Jae
Sim Jae-Yoon
Harness & Dickey & Pierce P.L.C.
Samsung Electronics Co,. Ltd.
Zweizig Jeffrey
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