Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2007-06-05
2007-06-05
Mai, Son L. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S226000, C327S538000, C327S543000
Reexamination Certificate
active
11202880
ABSTRACT:
There are provided a voltage level control circuit with a reduced power consumption and a method of controlling the same. When a signal “A” is in a “L” level and a signal PL entered from the outside of the voltage level control circuit becomes “H” level, a latch signal La outputted from a latch (11) becomes “H” level, whereby NFETs (14, 17, 24) turn ON. A voltage dividing circuit comprising resistances (12, 13) and current mirror differential amplifiers (20, 27) are placed in active states to output “H” as a signal A which controls a boost voltage Vbt (word line driving voltage. As the boost voltage Vbt is increased and reaches to a reference voltage Vref2,a voltage V2becomes “H”, whereby the signal A becomes “L”. After the signal A become “L”, the latch (11) is made through. At this time, the signal PL is “L”, the latch signal La outputted from the latch (11) becomes “L”, whereby the NFETs (14, 7, 24) turn OFF. As described here, the NFETs (14, 7, 24) is kept OFF in the other time period than when needed, in order to reduce the power consumption.
REFERENCES:
patent: 5258950 (1993-11-01), Murashima et al.
patent: 5295112 (1994-03-01), Taniguchi
patent: 5352935 (1994-10-01), Yamamura et al.
patent: 5696465 (1997-12-01), Ishizuka
patent: 5696730 (1997-12-01), Slezak et al.
patent: 5986959 (1999-11-01), Itou
patent: 6184744 (2001-02-01), Morishita
patent: 6313694 (2001-11-01), Sohn
patent: 6339357 (2002-01-01), Yamasaki et al.
patent: 6456155 (2002-09-01), Takai
patent: 6525587 (2003-02-01), Makino
patent: 6751132 (2004-06-01), Jang et al.
patent: 61-294695 (1986-12-01), None
patent: 62-140294 (1987-06-01), None
patent: 3-46184 (1991-02-01), None
patent: 4-205883 (1992-07-01), None
patent: 6-349271 (1994-12-01), None
patent: 7-130171 (1995-05-01), None
patent: 10-340597 (1998-12-01), None
patent: 11-66855 (1999-03-01), None
Nakagawa Atsushi
Takahashi Hiroyuki
Mai Son L.
Muirhead and Saturnelli LLC
NEC Electronics Corporation
LandOfFree
Internal voltage level control circuit and semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Internal voltage level control circuit and semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Internal voltage level control circuit and semiconductor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3835415