Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2000-09-26
2002-08-20
Ho, Hoai V. (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C438S014000, C438S018000, C438S048000
Reexamination Certificate
active
06437364
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention generally relates to a device for semiconductor integrated circuits, and in particular to a device for internal probe pads.
2. Description of the Prior Art
Typically, Integrated Circuits have numerous contacts that provide interfaces between the circuits within the die and the outside world. The contacts are used for bond pads to which bond wires are connected. The bond wires are also connected to the lead frame. The contacts may be used for various signals including those for addressing, data(DQ), VCC(power), VSS(ground), and control. However, the contacts are extremely small or tiny. As such, it is impractical and expensive to provide direct connections between each of the contacts and probes used in testing, or repairing of the IC. Probe pads that are much larger than die contacts have been placed on, for example, the edge of the wafer. However, the sheer volume of contacts limits the number of contacts to which probe pads may be practically connected.
Failure analysis typically includes applying selected voltages to circuit inputs and examining selected output voltage levels, either through the use of a functional tester or a mechanical probing system. A mechanical probing system allows the failure analysis technician to apply probes to establish electrical connections to selected locations within the circuitry on a failed chip. However, this work is difficult and time consuming. The technician must visually locate the point of interest on the failed chip under a microscope, among thousands or millions of transistors and perhaps four or five layers of metal, and then manually position a probe at that point. Only a handful of probes can be applied using manual systems due to mechanical space limitations. The limited number of probes available limits the types of failure testing that can be accomplished in this manner.
An integrated circuit consists of electronic devices electrically coupled by interconnects. Interconnects are patterned from conductive layers formed on or above the surface of a silicon substrate. One or more conductive layers may be patterned to form one or more levels of interconnects vertically spaced from each other by one or more interlevel dielectric layers. Common materials for interlevel dielectric layers include silicon dioxide, silicon nitride, and polyimide. Dielectric-spaced interconnect levels allow formations of densely patterned devices on relatively small surface areas. Interconnects on different levels are commonly coupled electrically using via plugs formed in vias. Interconnect lines may be formed by stacking layers of various conductive materials on top of one another. Currently, such metal stacks commonly include titanium (Ti), aluminum (Al), copper (Cu), tungsten (W), and alloys of these metals.
In the prior art, a probe pad is connected to only one contact, so that it needs many probes to place the die into a certain mode. It is inconvenient to observe whether hot spots or emission spots occur in a die by a microscope while many probes are used. Especially in some packages, such as LOC (lead on chip), too many probes make the die more difficult to be tested.
SUMMARY
It is an object of the invention to reduce the number of probe pads which are used while a die is placed into a mode.
It is another object of the invention that a die can be placed to a mode by fewer probes.
It is still another object of the invention to make the observation of defects more convenient in failure analysis.
According to the foregoing objects, the present invention provides a circuitry within a die. The circuitry comprises a plurality of probe pads placed in the last metal layer of the die. Each probe pad is divided into several conductive regions, and each conductive region is selectively connected to one of the contacts of the internal circuitry within the die by interconnects. The circuitry can be placed into a mode by supplying a signal to at least one probe pad of the plurality of probe pads. In addition, a passivation layer may be deposited on the surface of the last metal layer. There are many openings formed in the passivation layer to explore these probe pads.
The present invention provides a method to place the circuitry within a die into a mode by internal probe pads. Firstly, a plurality of probe pads are formed in the last metal layer of a die. Each probe pad is divided into several conductive regions, and each conductive region is selectively connected to one of the contacts of the internal circuitry within the die by interconnects. Secondly, the circuitry within the die is placed into a mode by supplying signals to parts of the plurality of probe pads, wherein at least one probe pad is used to transmit the signals into the circuitry and another one of the probe pads is grounded.
The arrangement of probe pads on a die is not limited. The number of conductive regions in each probe pad is at least two. The shape and arrangement of conductive regions are also not restricted.
REFERENCES:
patent: 5391892 (1995-02-01), Devereaux et al.
patent: 5623214 (1997-04-01), Pasiecznik, Jr.
patent: 5936876 (1999-08-01), Sugasawara
patent: 6094056 (2000-07-01), Bardsley et al.
patent: 6133054 (2000-10-01), Henson
patent: 6312963 (2001-11-01), Chou et al.
patent: 6323048 (2001-11-01), Chevallier
Ho Hoai V.
Huynh Andy
Powell Goldstein Frazer & Murphy LLP
United Microelectronics Corp.
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