Internal ESD protection structure with contact diffusion

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257408, 257382, H01L 2362

Patent

active

059124946

ABSTRACT:
An ESD protected structure and method of its fabrication are disclosed. A heavily doped polycrystalline silicon region of a first conductivity type is disposed on a substrate surface and is connected to a power supply voltage. A lightly doped region, of the first conductivity type, is disposed below the substrate surface and below the polycrystalline silicon region. A first heavily doped region, of the first conductivity type, of a first MOS device is disposed below the substrate surface, and contained entirely within the lightly doped region. A second heavily doped region, of the first conductivity type, of a second MOS device, is disposed below the substrate surface, and separated from the first region by a portion of the lightly doped region and a second conductivity type doped portion of the substrate. The separation of the first and second regions by a portion of the lightly doped region increases a turn-on voltage of a parasitic bipolar junction device that includes the first and second regions, the portion of the lightly doped region and the second conductivity type doped portion of the substrate. The increase in turn on voltage, in turn, tends to prevent the bipolar junction device from turning on, during an ESD event, before an ESD protection device that protects the structure from ESD events which occur within the power supply voltage. According to the fabrication process, the heavily doped polycrystalline silicon region is formed on the substrate surface and impurities are thermally diffused therefrom below the substrate surface to form the lightly doped region.

REFERENCES:
patent: 5569947 (1996-10-01), Iwasa et al.
C. Duvvury, R. Rountree & O. Adams, Internal Chip ESD Protection Beyond the Circuit, I.E.E.E Trans. Of Elec. Devs., vol. 35, No. 12, pp. 2133-2138, Dec., 1988.
J.LeBlanc & M. Chaine, Proximity Effects of "unused" Output Buffers on ESD Performance, I.E.E.E. IRPS Proc., pp. 327-330 (1991), Dec. 1991.

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