Internal ESD protection circuit for semiconductor devices

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

257399, 257400, 257409, 257493, 257494, 257495, H01L 2362, H01L 2976, H01L 2994

Patent

active

057510423

ABSTRACT:
An internal electrostatic discharge (ESD) protection circuit for semiconductor devices defines a structure for protecting adjacent n-channel devices. The first n-channel device includes a pair of n+ regions defining source and drain regions wherein the drain region is connected to a positive power supply terminal (V.sub.DD). The second, adjacent, n-channel device also includes a pair of n+ regions forming source and drain regions, respectively, wherein the source region of the second n-channel device is connected to a negative power supply terminal (V.sub.SS). The drain of the first n-channel device is laterally spaced, and isolated from the source of the second n-channel device by a thick field oxide region. The novel structure includes forming an N-conductivity type well that substantially overlaps the drain n+ region of the first n-channel device and extends toward the n+ region that forms the source of the second n-channel device. The N-well is doped to a lower density than the n+ regions, and further, is formed into the substrate to a depth that is substantially larger than the depth of the n+ regions. The N-well substantially increases the junction breakdown voltage of the device. Alternately, a p+ conductivity guard ring is disposed intermediate the n+ region forming the drain of the first n-channel device, and the n+ region forming the source of the second n-channel device to thereby reduce the current gain of a parasitic NPN bipolar transistor formed between the two n-channel devices. The decreased current gain prevents snapback triggered by an ESD event.

REFERENCES:
patent: 4481521 (1984-11-01), Okumura
patent: 4821096 (1989-04-01), Maloney
patent: 4893157 (1990-01-01), Miyazawa et al.
patent: 4922317 (1990-05-01), Mihara
patent: 4990802 (1991-02-01), Smooha
patent: 5019888 (1991-05-01), Scott et al.
patent: 5043782 (1991-08-01), Avery
patent: 5140401 (1992-08-01), Ker et al.
patent: 5168340 (1992-12-01), Nishimura
patent: 5182220 (1993-01-01), Ker et al.
patent: 5218222 (1993-06-01), Roberts
patent: 5289334 (1994-02-01), Ker et al.
patent: 5329143 (1994-07-01), Chan et al.
patent: 5386135 (1995-01-01), Nakazato
patent: 5406105 (1995-04-01), Lee
patent: 5406513 (1995-04-01), Canaris et al.
C. Duvvury, R.N. Rountree, Y. Fong, and R.A. McPhee, ESD Pheonomena And Protection Issues In CMOS Output Buffers 1987, 174-180, EECS Dept. University of California at Berkley, Berkley, California.
Charvaka Duvvury, Robert N. Rountree and Olen Adams, Internal Chip ESD Pheonomena Beyond The Protection Circuit Dec. 1988, vol. 35, No. 12, IEEE Transactions on Electron Devices.
T. Polgreen and A. Chatterjee, Emproving The ESD Failure Threshold Of Silicided aMOS Output Transistors By Ensuring Uniform Current Flow, 1989, 167-174, ESD Symposium Proceedings.
Amitava Chatterjee and Thomas Polgreen, A Low-Voltage Triggering SCR For On-Chip ESD Protection At Output And Input Pads, Jan. 1991 vol. 12, No. 1, 21-22, IEEE Electron Device Letters.
Charvaka Duvvury, Carlos Diaz and Tim Haddock, Achieving Uniform nMOS Device Power Distribution For Sub-Micron ESD Reliability, 1992, 131-134, IEEE.
Steven H. Voldman, ESD Protection in a Mixed Voltage Interface and Multi-Rail Disconnected Power Grid Environment In 0.50- and 0.25-.mu.m Channel Length CMOS Technologies, 1994, 125-134, EOS/ESD Symposium.
S. Dabral, R. Aslett and T. Maloney, Core Clamps For Low Voltage Technologies, 1994, 141-149, EOS/ESD Symposium.
Steven H. Voldman and Gianfranco Gerosa, Mixed-Voltage Interface ESD Protection Circuits For Advanced Microprocessors in Shallow Trench and Locos Isolation CMOS Technologies, 1994, 277-280, IEEE.
Mark D. Jaffe and Peter E. Cottrell, Electrostatic Discharge Protection in a 4-MBIT Dram, 1-6, IBM General Technology Division, Essex Junction, VT.
J.P. LeBlanc and M.D. Chaine, Proximity Effects Of "UnUsed" Output Buffers on ESD Performance, 327-330, Texas Instruments Incorporated, Houston, Texas.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Internal ESD protection circuit for semiconductor devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Internal ESD protection circuit for semiconductor devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Internal ESD protection circuit for semiconductor devices will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-983287

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.