Internal command signal generator and method therefor

Details Internal command signal generator and method therefor Internal command signal generator and method therefor

1999-12-23

2002-09-10

Ray, Gopal C. (Department: 2181)

Electrical computers and digital data processing systems: input/

Interrupt processing

C710S052000, C711S100000, C365S230080, C365S233100

Reexamination Certificate

active

06449674

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an internal command signal generator and a method therefor, which generate internal command signal for an internal circuit operation after receiving external control signal in a synchronous memory device. More particularly, it relates to an internal command signal generator and a method therefor, which perform a decoding of internal command signal during a delay time required to ensure a setup and hold time margin about internal clock signal, thus greatly reduce a data access time and embody a high-speed synchronous memory element.
2. Description of the Prior Art
Generally, a computer system is comprised of a central processing unit (CPU), peripheral Input/Output unit, and memory unit. A main supply source of a main memory unit of computer being presently used has a plurality of requirements (that is, a low price per a bit, a response characteristic suitably responding to a high-speed operation of CPU, and a high integration to reduce a capacity of entire system). As a result, to satisfy the above requirements, the main supply source is being changed to a synchronous dynamic random access memory (DRAM).
The synchronous DRAM is synchronized to an edge of a main
30
clock signal used in computer CPU and peripheral chip-set, and thus performs an input/output operation. A memory cell of the synchronous DRAM is comprised of a matrix structure of 2
N
(Row)×2
M
(Column) in the same manner as a general DRAM.
Therefore, in order to read a stored data of the synchronous DRAM, N row addresses are firstly input by a row command signal, and are then decoded. In this way, a desired one row (i.e., word line) among row addresses of 2
N
is selected and then enabled.
Thereafter, M external input column addresses are decoded by a column command signal in order to select one bit line among column addresses of 2
M
. Input/output operation of a selected bit line data according to a read command or a write command is achieved.
At this time, a time required to generate a data from an external clock signal(ext_clk) wherein external control signals (i.e., /RAS, /CAS, /WE . . . ) are input to generate the column command signal is called a data access time (tAA). Lowering the data access time (tAA) is a very important matter in a high frequency operation.
FIG. 1
is a block diagram of a conventional internal command signal generator, and shows a case that an internal command signal is a column command signal. Hereinafter, a discussion focus is placed on a generation of internal column command signal.
As shown in
FIG. 1
, in order to generate a command signal for an internal operation control of a memory element, the conventional internal command signal generator includes: a plurality of input buffer units
10
which buffer each of a plurality of external control signals (/RAS, /CAS, /WE. . . ) of TTL level with a CMOS level signal suitable to an internal circuit operation; a clock buffer unit
20
for generating an internal clock signal (int_clk) by buffering an external clock signal (ext_clk); a plurality of delay units
30
for delaying the external control signals generated from the input buffer units
10
in order to ensure a setup and hold time margin about the internal clock signal (int_clk); a plurality of latch units
40
which synchronize each control signal delayed by the delay units
30
to the internal clock signal (int_clk) generated from the clock buffer unit
20
, and generate pulse signals (in_pulse_
1
~in_pulse_n) internally used; and a command decoder unit
50
for receiving each internal pulse signal (in_pulse_
1
~in_pulse_n) generated from the latch units
40
, and generating internal column command signals (casatv, icasatv).
FIG. 2
illustrates an operation timing diagram of the conventional internal command signal generator shown in FIG.
1
.
As shown in FIG.
2
(
c
), external input command control signals (/RAS,/CAS,/WE. . . ) of TTL level pass through the input buffer units
10
, and are then changed to a buffering signal of CMOS level as shown in FIG.
2
(
d
). The buffering signal is synchronized to the internal clock signal (int_clk). Therefore, an internal pulse signal (in_pulse) shown in FIG.
2
(
e
) is generated.
At this time, the buffering signal shown in FIG.
2
(
d
) has a predetermined delay time (Dt
1
) for ensuring a setup and hold time margin, prior to a synchronization about the internal clock signal (int_clk) shown in FIG.
2
(
b
).
Accordingly, internal pulse signal (in_pulse) shown in FIG.
2
(
e
) becomes generated after the delay time (Dt
1
). Then, the command decoder unit
50
combines the internal pulse signals, thereby generating CAS activation control command signal (casatv) being used as an internal column command signal.
In addition, the command signal generator of
FIG. 1
receives the internal clock signal (int_clk) under the condition that a signal (yburst_flag) that the internal column comand signal is latched by a burst controller (not shown) is enabled, thereby generating another internal column command signal (icasatv). If the internal column command signal generator receives two internal column command signals (casatv, icasatv), a column operation starts.
However, the aforementioned conventional internal column command signal generator which generates an internal command signal by a combination of internal pulse signals (in_pulse_
1
~in_pulse_n) generated by a synchronization to the internal clock signal (int_clk) has two kinds of time loss problems.
Firstly, before a control signal buffered by the input buffer is synchronized to the internal clock signal (int_clk), a predetermined delay time is required to ensure the setup and hold time margin about the internal clock signal (int_clk).
Secondly, during a read operation, if a read interrupt command is input when an internal column operation is performed by receiving the internal column command signals (casatv, icasatv), the internal column command signal (icasatv) should be disabled to prevent an internal operation. Accordingly, a disable path is added to a generation part of the internal column command signal (icasatv).
An interrupt signal for preventing a problem that the internal column command signal (icasatv) is generated after the CAS activation control command signal (casatv) is additionally made, so that an enable operation of a column address predecoding control signal (ypc) is prevented. In this case, a time margin about the interrupt signal should be considered.
In conclusion, according to the conventional internal command signal generator and method thereof, a data access time becomes increased due to an additional delay time, a high-speed operation of a synchronous memory element becomes limited.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to an internal command signal generator and a method therefor that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
It is an objective of the present invention to provide an internal command signal generator and a method therefor which greatly reduce a generation time of internal command signal by reducing a data access time, thereby achieving a high-speed operation.
To achieve the above objective, an internal command signal generator according to the present invention includes: a first buffer unit for buffering an external input command control signal with a signal level suitable to an internal circuit operation; a second buffer unit for buffering an external clock signal with an internal clock signal suitable to an internal circuit operation; a delay unit for delaying an output signal of the first buffer unit by a predetermined time in order to ensure a setup and hold time margin about the internal clock signal; a command decoder unit for receiving buffering signals generated from the first buffer unit, previously performing a decoding operation by combining the buffering signals during a constant delay time determined by the delay unit, and generating an interna

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