Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate
2000-03-01
2001-06-05
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
C327S154000, C327S175000
Reexamination Certificate
active
06242960
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a synchronous dynamic random access memory (SDRAM), and more particularly, to a circuit for generating an internal clock signal synchronized with an external clock signal for use in SDRAMs.
2. Description of the Related Art
In synchronous dynamic random access memories (SDRAMs), control signals for data input and output are generated based on an external clock signal which is provided by an external system. In particular, internal signals of an SDRAM are generated based on an internal clock signal which is obtained from an external clock signal provided by an external system. Thus, control signals for data input/output operation in an SDRAM is generated based on the internal clock signal, which may be a pulse signal.
Generally, an internal clock signal generating circuit has several delay units. The delay units are used to activate an internal clock signal for a predetermined period of time and then deactivate the internal clock signal. That is, the internal clock signal is activated in response to a leading edge of an external clock signal and deactivated in response to a pulse signal obtained by delaying the external clock signal for a predetermined period of time using the delay units. The width of an activation period of the internal clock signal is determined by the amount of time for which the delay units delay the internal clock signal. Also, in SDRAMs, it is desirable that the activation period of the internal clock signal is long enough to provide a margin between internal signals in an SDRAM. Thus, delay times of the delay units should be greater than or equal to a predetermined period of time.
However, a conventional internal clock signal generating circuit has a problem in that an internal clock signal can be falsely or not generated when an external clock signal has an activation period which is shorter than required. For example, an internal clock signal is generated in synchronization with an external clock signal, that is, one cycle of the internal clock signal should be generated in response to every cycle of the external clock signal. When an external clock signal having an activation period which departs from a predetermined value, due to factors such as noise generated in a system, is applied to a memory device, a corresponding internal clock cycle may not be generated before the start of a next cycle of the external clock signal. As a result, the internal clock signal may not be generated corresponding to every cycle of the external clock signal. Thus, the internal clock signal is not synchronized with the external clock signal.
There is another problem in that an internal clock signal generated by a conventional internal clock signal generating circuit is not synchronized with an external clock signal when an activation period of the external clock signal becomes shorter than normal, a condition possibly caused by high-speed operation of the system.
Therefore, it is desired that a frequency characteristic of an internal clock signal generating circuit is improved so that the internal clock signal generating circuit can be applied to a system which operates at high frequencies.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a circuit for generating an internal clock signal synchronized with an external clock signal for use in a memory device.
To achieve the above and other objects, the present invention provides a circuit for generating an internal clock signal, including a pulse generation circuit for receiving a reference clock signal which is obtained from and synchronized with an external clock signal, and generating an internal clock signal. The pulse generation circuit includes a pulse generation unit for generating a pulse signal which is activated in response to a rising edge of a first delay signal obtained by delaying the reference clock signal by a first delay time, and deactivated in response to a falling edge of a second delay signal obtained by delaying the reference clock signal by a second delay time which is shorter than the first delay time, and a driving unit for generating the internal clock signal which is activated in response to a falling edge of the reference clock signal and deactivated in response to a rising edge of the pulse signal. The pulse generation unit includes a first delay unit for receiving and delaying the reference clock signal by the first delay time to generate the first delay signal, a second delay unit for receiving and delaying the reference clock signal by the second delay time to generate the second delay signal, and a logic unit receiving the first and second delay signals from the first and second delay units, respectively, for performing a predetermined logic operation with respect to the first and second delay signals to generate the automatic pulse signal. The first and second delay units are configured such that the difference between the first delay time in the first delay unit and the second delay time in the second delay unit is less than an activation period of the external clock signal. The driving unit also includes a pull-up unit for activating the internal clock signal in response to the reference clock signal and the automatic pulse signal, and a pull-down unit for deactivating the internal clock signal in response to the automatic pulse signal.
The internal clock signal generating circuit with the above features according to the present invention can generate a normal internal clock signal even if it is applied to a system which operates at high speed.
REFERENCES:
patent: 5264737 (1993-11-01), Oikawa
patent: 5396110 (1995-03-01), Houston
patent: 5600274 (1997-02-01), Houston
Cox Cassandra
F. Chau & Associates LLP
Samsung Electronics Co,. Ltd.
Tran Toan
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