Internal clock multiplication for test time reduction

Details Internal clock multiplication for test time reduction Internal clock multiplication for test time reduction

1999-09-27

2000-05-30

Tran, Andrew Q.

Static information storage and retrieval

Read/write circuit

Testing

365233, 365236, 36518908, 36523003, 714719, 714718, G11C 2900

Patent

active

060698292

ABSTRACT:
A circuit is designed with a clock circuit (215, 217) coupled to receive a control signal having a first logic state and a second logic state. The clock circuit produces a first clock signal (CLK) response to the first logic state and a second clock signal (*CLK) in response to the second logic state. The second clock signal has a frequency at least twice a frequency of the first clock signal. An address counter (221) is coupled to receive one of the first and second clock signals. The address counter produces a sequence of address signals corresponding to the one of the first and second clock signals. An array of memory cells is arranged to produce a sequence of data bits corresponding to the sequence of address signals. A logic circuit (235, 239, 240) is coupled to receive the sequence of data bits. The logic circuit produces a logical combination of the sequence of data bits.

REFERENCES:
patent: 5991213 (1999-11-01), Cline et al.
patent: 5995426 (1999-11-01), Cowles et al.
patent: 6009026 (1999-12-01), Tamlyn et al.
patent: 6014336 (2000-01-01), Powell et al.
patent: 6016561 (2000-01-01), Roohparvar et al.
patent: 6026039 (2000-02-01), Kim et al.

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