Internal clock generation circuit of semiconductor device and me

Details Internal clock generation circuit of semiconductor device and me Internal clock generation circuit of semiconductor device and me

1998-02-17

2000-11-28

Elms, Richard

Static information storage and retrieval

Addressing

Sync/clocking

36518905, 3652335, G11C 800

Patent

active

061544159

ABSTRACT:
An internal clock generation circuit for a semiconductor device and a method for generating an internal clock signal are disclosed. The internal clock generation circuit reduces the power consumed by a semiconductor device by generating internal clock pulses only when they are necessary for the operation of the device. The internal clock generation circuit includes a clock buffer, an internal clock generation unit, a chip selection buffer and an internal clock control unit. The clock buffer converts the voltage level of an external clock signal. The internal clock generation unit receives the output from the clock buffer and generates an internal clock signal only when a control signal is enabled. The chip selection buffer converts the voltage level of a chip selection signal which is active when the device is enabled. The internal clock control unit receives the output from the chip selection buffer and generates the control signal which is activated when the chip selection signal is active. The internal clock control unit also activates the control signal when either a column address signal or a latency signal is enabled. The internal clock signal is disabled when the control signal is disabled, and enabled when the control signal is enabled and at the same time the external clock signal is enabled.

REFERENCES:
patent: 5301165 (1994-04-01), Ciraula et al.
patent: 5748553 (1998-05-01), Kitamura
patent: 5808961 (1998-09-01), Sawada
patent: 5880998 (1999-03-01), Tanimura et al.
patent: 5898331 (1999-04-01), Fujita

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