Internal clock generating circuit for clock synchronous type sem

Details Internal clock generating circuit for clock synchronous type sem Internal clock generating circuit for clock synchronous type sem

1997-07-25

1998-09-15

Dinh, Son T.

Static information storage and retrieval

Addressing

Sync/clocking

365194, 3652335, G11C 800

Patent

active

058089616

ABSTRACT:
An internal clock signal generation circuit includes a portion to generate an internal clock signal (intCLK) generated in synchronization with an external clock signal, a pulse width setting circuit which sets the pulse width of the internal clock signal depending the operation condition. By adjusting the pulse width of the internal clock signal to generate depending upon the operation condition, an internal clock signal having an optimum pulse may be readily generated. An internal clock signal having an optimum pulse width depending upon the operation condition may be generated accordingly, and internal data may be accurately transferred as a result.

REFERENCES:
patent: 5581512 (1996-12-01), Kitamura
patent: 5619463 (1997-04-01), Malhi
patent: 5666321 (1997-09-01), Schaefer
patent: 5666324 (1997-09-01), Kosugi et al.

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