Intermediate output buffer circuit for semiconductor memory devi

Details Intermediate output buffer circuit for semiconductor memory devi Intermediate output buffer circuit for semiconductor memory devi

1976-12-29

1979-03-13

Konick, Bernard

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

307DIG3, 307DIG4, 365203, G11C 706

Patent

active

041445902

ABSTRACT:
A random access memory device of the MOS integrated circuit type employs an array of rows and columns of one-transistor storage cells with sense amplifier circuits at the center of each column and an intermediate output buffer having inputs connected to both sides of the column lines. The intermediate output buffer is a bistable circuit wherein the load transistors have clock voltages applied to their gates after an initial sensing period, so the initial sensing of data on the column lines is done without loads. After this initial period, the load transistors are turned on by booting capacitors. Then, transistors shunting the gates of the load devices to the sense nodes function to turn off the load device on the zero logic level side. The gates of these shunting transistors are each controlled by the voltages on the sense node on the opposite side of the bistable circuit.

REFERENCES:
patent: 3678473 (1972-07-01), Wahlstrom
patent: 3838295 (1974-09-01), Lindell
patent: 3983412 (1976-09-01), Roberts et al.
patent: 3992704 (1976-11-01), Kantz
patent: 4031522 (1977-06-01), Reed et al.
patent: 4039861 (1977-08-01), Heller et al.
patent: 4077031 (1978-02-01), Kitagawa et al.
Chu et al., "Low-Power, High-Speed Sense Latch", IBM Tech. Disc. Bull., vol. 17, No. 9, pp. 2582-2583, Feb. 1975.
Bishop et al., "High-Sensitivity High-Speed FET Sense Latch", IBM Tech. Disc. Bull., vol. 18, No. 4, pp. 1021-1022, Sept. 1975.
Arzubi, "Sense Amplifier for Capacitive Storage", IBM Tech. Disc. Bull., vol. 19, No. 2, pp. 407-408, Jul. 1976.

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