Intermediate memory array with a parallel port and a buffered se

Details Intermediate memory array with a parallel port and a buffered se Intermediate memory array with a parallel port and a buffered se

1984-06-29

1988-01-05

Harkcom, Gary V.

Boots, shoes, and leggings

365219, G06F 1300, G11C 1300

Patent

active

047180390

ABSTRACT:
A dual ported buffer memory for a hierarchical memory, cmprising an addressable memory array for multi-bit words and a multi-bit register. Data is transferred a word at a time between the memory array and a multi-bit bus to a higher level in the memory system and between the memory array and the register. Data is transferred a bit at a time between the register and a single serial line. Concurrent operations are possible for transfers between the memory array and the parallel bus and between the register and the serial line.

REFERENCES:
patent: 3166739 (1965-01-01), Haynes
patent: 4402067 (1983-08-01), Moss et al.
patent: 4489381 (1984-12-01), Lavallee et al.

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