Intermediary circuit between a low voltage logic circuit and a h

Details Intermediary circuit between a low voltage logic circuit and a h Intermediary circuit between a low voltage logic circuit and a h

1994-01-14

1995-12-05

Westin, Edward P.

Electronic digital logic circuitry

Interface

Supply voltage level shifting

326 68, 326 81, H03K 19094, H03K 326

Patent

active

054732689

DESCRIPTION:

BRIEF SUMMARY
The present invention concerns an intermediary circuit between an integrated low voltage logic circuit and a high voltage output stage for controlling transducers, plasma screens and electromechanical actuators, wherein said high voltage output stage comprises at least two transistors with channel N and channel P, respectively, assembled according to standard CMOS technology.
In the context of the present invention, "high voltage" means any voltage which is higher than the "nominal" or "normal" voltage used in a technology, including tolerance. This nominal or normal usage voltage corresponds to the voltage supply normally applied to the standard MOS components and/or circuits assembled in this technology which the latter can withstand without damage during intermittent or continuous use.
Generally speaking, receptors and actuators are designed to establish communication between the circuits which process a signal and their environment. The receptors provide external data to these circuits. The actuators transform low power signals and low voltage signals into external activity, such as, for example, communicating information in a car. During the last few years power circuits with such intelligence known as "smart power electronics" have proven very useful for multiple applications.
In order to combine low voltage logic circuits based on standard complementary metal oxide semiconductor technology manufacturing methods known as "standard CMOS" with high voltage "CMOS" output stages on the same integrated circuit, while also maintaining low production costs, an attempt has been made to produce metal oxide transistors with a field effect, which are called MOSFETs, with high voltage and totally compatible with so-called standard low voltage technology. This has been made possible by a novel combination of layers existing within the standard CMOS technology, which remains unchanged. The creation of slightly doped buffer zones between the channel and the drain and the use of field electrodes and protective screens result in devices capable of withstanding high voltage.
The resulting high voltage MOSFETs have the same threshold voltage V.sub.T as their low voltage counterparts, but are capable of supporting elevated drain-source voltage V.sub.ds in excess of 30 V. However, these components are limited to weak gate-source voltage V.sub.os because standard gate oxides are thin, thereby causing problems of reliability and efficiency in an intermediary circuit of the type described above designed to be interposed between a low voltage logic circuit and a high voltage output.
The topology of high voltage CMOS reverse-outputs is similar to the conventional reverse CMOS topology in which the source and the mass of the transistor with channel N are connected to a ground V.sub.ss, the source and the mass of the transistor with channel P are connected to the positive high voltage supply V.sub.DDH and the drains of the two transistors are connected together at the output. However, an essential difference is apparent when controlling gates with a low voltage signal issuing from the logic circuit. The gates of the high voltage MOSFET transistor with channel N called an NMOS-HT transistor can be controlled easily by the levels of the low voltage logic 0/V.sub.DD, while the gates of the high voltage MOSFET transistor with channel P called the PMOS-HT transistor requires inserting a level in order to be activated between V.sub.DDH -V.sub.DD and V.sub.DDH to respect the relative voltage conditions between the gates and the source V.sub.os.
One solution for inserting a level could be based on the use of a condenser mounted between the gates of the NMOS transistor and that of the high voltage PMOS transistor. However, this solution has not proven reliable. In practice it is difficult to maintain the gates-source voltage V.sub.os within acceptable tolerances during the transitional phases involving engagement of voltage V.sub.DDH or during long periods of inactivity.
Various prior publications describe voltage shift circuits, but no

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NEC Research & Development; No. 94, Jul. 1989, Tokyo, JP pp. 29-35; M. Nakano et al. 'Full-Complementary High-Voltage Drive ICs for Flat Display Panels' see figures 1C and 3; paragraphs 1 and 2.

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