Interlevel dielectric with air gaps to lessen capacitive...

Details Interlevel dielectric with air gaps to lessen capacitive... Interlevel dielectric with air gaps to lessen capacitive...

1998-01-27

2001-03-27

Meier, Stephen D. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

With means to control surface effects

Insulating coating

C257S637000, C257S758000

Reexamination Certificate

active

06208015

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor fabrication and more particularly to a dielectric material placed between semiconductor interconnect lines on the same or on different levels such that the dielectric contains air gaps and trenches arranged between interconnect lines. The air gaps or trenches are void of dielectric thereby decreasing the overall permittivity of the interlevel or interlayer dielectric.
2. Description of the Relevant Art
An integrated circuit includes numerous conductors extending across the topography of a monolithic substrate. A set of interconnect lines (or conductors) which serve to electrically connect two or more components within a system is generally referred to as a “bus”. A collection of voltage levels are forwarded across the conductors to allow proper operation of the components. For example, a microprocessor is connected to memories and input/output devices by certain bus structures. There are numerous types of busses which are classified according to their operation. Examples of well-known types of busses include address busses, data busses and control busses.
Conductors within a bus generally extend parallel to each other across the semiconductor topography. The conductors are isolated from each other and from underlying conductive elements by a dielectric, a suitable dielectric being, for example, silicon dioxide (“oxide”). Conductors are thereby lithography patterned across the semiconductor topography, wherein the topography comprises a substrate with a dielectric placed thereon. The topography can also include one or more layers of conductors which are sealed by an upper layer of dielectric material. Accordingly, the layers of conductors overlayed with a dielectric present a topography upon which a subsequent layer of conductors can be patterned.
Conductors are made from an electrically conductive material. Suitable materials may include Al, Ti, Ta, W, Mo, polysilicon, or a combination thereof. Suitable substrates may include any type of material which can retain dopant ions and the isolated conductivity regions brought about by those ions. Typically, the substrate is a silicon-based material which receives p-type or n-type ions.
Generally speaking, interconnect lines (or conductors) are fashioned upon the topography and spaced above an underlying conductor or substrate by a dielectric of thickness T
d1
. Each conductor is dielectrically spaced from other conductors within the same level of conductors by a distance T
d2
. Accordingly, conductor-to-substrate capacitance C
LS
(i.e., capacitance between conductors on different levels) is determined as follows:
C
LS
≈&egr;W
L
L/T
d1
  (1)
Further, the conductor-to-conductor capacitance C
LL
(i.e., capacitance between conductors on the same level) is determined as follows:
C
LL
≈&egr;T
c
L/T
d2
  (2)
, where &egr; is the permittivity of the dielectric material (the dielectric material between the conductor and substrate or the dielectric material between conductors), W
L
is the conductor width, T
c
is the conductor thickness, and L is the conductor length. Resistance of the conductor is calculated as follows:
R=(pL)/W
L
T
c
  (3)
, where p represents resistivity of the conductive material, and T
c
is the interconnect thickness. Combinations of equations 1 and 3, and/or equations 2 and 3 indicate the propagation delay of a conductor as follows:
RC
LS
≈p&egr;L
2
/T
c
T
d1
RC
LL
≈p&egr;L
2
/W
L
T
d2
Propagation delay is an important characteristic of an integrated circuit since it limits the speed (frequency) at which the circuit or circuits can operate. The shorter the propagation delay, the higher the speed of the circuit or circuits. It is therefore important that propagation delay be minimized as much as possible within the geometric constraints of the semiconductor topography.
Propagation delay is a function of both capacitance C
LS
as well as capacitance C
LL
. Accordingly, propagation delay is determined by parasitic capacitance values (C
LL
) between laterally spaced conductors, and parasitic capacitance values (C
LS
) between vertically spaced conductors or between a conductor and the underlying substrate. As circuit density increases, lateral spacing between conductors decrease and capacitance C
LL
increases. Meanwhile, planarization mandates to some extent a decrease in vertical spacing. Shallow trench processing, recessed LOCOS processing, and multi-layered interlevel dielectrics bring about an overall reduction in vertical spacing and therefore an increase in C
LS
. Integrated circuits which employ narrow interconnect spacings thereby define C
LL
as a predominant capacitance, and integrated circuits which employ thin interlevel dielectrics define C
LS
as a predominant capacitance.
It is thereby important to minimize propagation delay especially in the critical speed path. Given the constraints of chemical compositions, it is not readily plausible to reduce the resistivity p of conductor materials. Geometric constraints make it difficult to increase conductor thickness T
c
or dielectric thickness T
d1
or T
d2
. Still further, instead of reducing length L of a conductor, most modern integrated circuits employ long interconnect lines which compound the propagation delay problems. Accordingly, a need arises for instituting a reduction in propagation delay but within the chemical and geometric constraints of existing fabrication processes. It is therefore desirable that a fabrication process be developed which can reduce propagation by reducing the permittivity &egr; of dielectric material. More specifically, the desired process must be one which reduces the permittivity of dielectric material arranged between horizontally displaced or vertically displaced conductors. As such, it would be desirable to employ a fabrication technique in which dielectrics between conductors achieve low permittivity.
SUMMARY OF THE INVENTION
The problems outlined above are in large part addressed by a dielectric fabrication process that produces a low permittivity between the interconnect lines of a first interconnect level (“intra-level permittivity”) and between the interconnect lines of a first interconnect level and the interconnect lines of a second interconnect level (“inter-level permittivity”). To reduce the intra-level permittivity, one embodiment of the process utilizes a first interconnect etch technique followed by an oxide formation technique that purposedly forms air gaps between closely spaced interconnect lines. A first interconnect level, preferably comprised of aluminum, is deposited on a wafer topography and then plasma etched in a chamber purposely depleted of polymers that would otherwise form passivating layers on the side walls of the interconnect. This etch technique results in a first interconnect that is “re-entrant” or undercut in the regions adjacent to the semiconductor topography. Next, a dielectric is deposited on the first interconnect. Preferably the dielectric is comprised of a silane source CVD oxide deposited at atmospheric pressure, or PECVD oxide deposited at low pressure. Deposition of these oxides upon sidewall re-entrant angles of the first interconnect produces poor coverage and therefore voids or air gaps are produced between the interconnect lines spaced close to one another. The oxide deposition process may be modified to enhance to air gap formation, if necessary.
Because the permittivity of air is less than the permittivity of a semiconductor dielectric, formation of an air gap within the dielectric causes a decrease in overall permittivity between interconnects. Reduction in the intra-level permittivity results in a reduction in the line-to-line capacitance C
LL
. Reduction in C
LL
is shown to reduce intra-level propagation delay RC
LL
. Formation of the air gap thereby reduces propagation delay and proves beneficial in meeting speed requirements within critical path interconnect lines, possibly interconnect lines spaced adjacent each other w

Affiliated with

Also associated with

Rating

Interlevel dielectric with air gaps to lessen capacitive... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Interlevel dielectric with air gaps to lessen capacitive..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interlevel dielectric with air gaps to lessen capacitive... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2446538