Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1996-06-05
1998-09-29
Bowers, Jr., Charles L.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438624, H01L 21316
Patent
active
058145559
ABSTRACT:
A reduced permittivity interlevel dielectric in a semiconductor device arranged between two levels of interconnect. The dielectric comprises a first dielectric layer preferably from a silane source deposited on a first level interconnect to form air gaps at midpoints between adjacent first interconnect structures, a second dielectric containing air gap trenches at spaced intervals across the second dielectric, and a third dielectric formed upon said second dielectric. A second interconnect level is formed on the third dielectric.
REFERENCES:
patent: 4675074 (1987-06-01), Wada et al.
patent: 5310700 (1994-05-01), Lien et al.
patent: 5393709 (1995-02-01), Lur et al.
Bandyopadhyay Basab
Brennan William S.
Dawson Robert
Fulford Jr. H. Jim
Hause Fred N.
Advanced Micro Devices , Inc.
Bowers Jr. Charles L.
Daffer Kevin L.
Whippue Matthew
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