Interlevel dielectric process

Adhesive bonding and miscellaneous chemical manufacture – Delaminating processes adapted for specified product – Delaminating in preparation for post processing recycling step

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156652, 156656, 156657, 156663, 437187, 437235, 437245, H01L 2100

Patent

active

051145308

ABSTRACT:
A process for the fabrication of integrated circuits, wherein the interlevel dielectric material is partially etched back prior to reflow. This provides a pre-reflow profile which prevents filament problems in subsequently-patterned conductor levels, and which also avoids cracking of the interlevel dielectric during reflow.

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Adams et al., "Planarization of Phosphorous-Doped Silicon Dioxide", J. Electrochem. Soc. (Feb. 1981) pp. 423-429.

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