Interleaving read and write operations on a bus and...

Details Interleaving read and write operations on a bus and... Interleaving read and write operations on a bus and...

1993-05-25

2004-10-19

Elmore, Reba I. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C711S157000, C711S168000

Reexamination Certificate

active

06807609

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a computer system and, more particularly, to a computer system which provides overlapping of read and write operations on a bus.
BACKGROUND OF THE INVENTION
High performance computer systems typically comprise a plurality of buses to transfer data between elements in the system. For example, a central processing unit (hereinafter “CPU”) may conduct data transfers to a memory array through intermediate control logic. In one configuration, there may be two bus arrangements—one which couples the CPU to the control logic and one which couples the memory array to the control logic.
The CPU reads or writes memory through the control logic by issuing the appropriate command with address and other information to the control logic and allowing the control logic to perform the requested task. In such a system, the CPU is then free to perform computational tasks instead of waiting for data to be fetched from memory. This is particularly true when a CPU issues a write to memory. In the prior art system, the CPU issues a write command and sends a block of data to the control logic for transfer to the memory array. At this point, the CPU is finished with the write operation. The data transferred to the control logic must then be written to the memory array.
In high performance computer systems, the memory modules which comprise the memory array cannot store data as fast as the control logic can deliver it across the bus. This speed constraint is generally attributable to the cycle time of the random access memory (hereinafter “RAM”) which comprises the memory on the memory modules. The cycle times of such devices are slow compared with the cycle time of the bus on which the control logic transfers the data to memory.
The prior art has addressed this problem by providing a buffer on a memory module that is large enough to hold a typical data block transferred from the control logic. This solution prevents tying up the bus minimizing any waste of bus bandwidth. The memory module writes the data stored in its buffer to its RAM at its own rate. The memory module, however, cannot be written to for a fixed period of time until its buffer is emptied.
While the prior art provides an adequate method for writing data to memory, there is a need for advancement. In particular, in a high performance computer system, a major bottleneck to processing speed is bus transfers. Thus, it is imperative to minimize bus transfers and also minimize the complexity of memory arrays to improve processing speed.
SUMMARY OF THE INVENTION
Accordingly, the present invention transfers write data from a CPU to a memory module in a plurality of data bursts interspaced by a preselected number of bus cycles which the memory modules use to absorb the issued data burst thereby reducing the buffer requirements of the memory module. The present invention utilizes the interspaced bus cycles to send pending read commands to another memory module to interleave read and write operations to thereby lower memory read latency and optimize the available bandwidth on the bus.
Generally, the present invention comprises a CPU coupled to a memory control logic device. The memory control logic device is also coupled to a memory array. The memory control logic device facilitates data transfers between the CPU and the memory array.
The present invention overcomes the disparity in speed between the cycle time of the bus coupling the memory array to the memory control logic device and the write latency of the memory module while reducing the buffer requirements of the memory module. The present invention implements a write to memory by first storing a data block received from a CPU in the memory control logic device. When the selected memory module, i.e., the memory module to which the write command is directed, becomes available, the memory control logic device transmits a block of data in a plurality of data bursts on the memory bus. The first data burst comprises a write command and a portion of the data block received from the CPU. The memory module latches this data in a latch and then transfers the data into its RAM. During this time when the memory module is transferring data from its latch to its RAM, the memory control logic device pauses a preselected amount of time in between each data burst to allow for the transfer of data from the latch to RAM and avoid the need for additional buffering on the memory module. The remaining portions of the block of data are transmitted from the memory control logic device to the selected memory module when the preselected amount of time has expired. The memory module again latches this data in its latch and transfers the data to its RAM.
The present invention utilizes the preselected amount of time between the plurality of data bursts to perform pending read operations with other memory modules. To accomplish this, the memory control logic device maintains a queue of pending read commands which it checks during the pause time. If there is a pending read to a nonselected memory module, i.e., a memory module not involved in the suspended write transaction, the memory control logic device transmits the read command to the selected memory module. By interleaving a read command in the preselected amount of pause time, the present invention reduces overall memory read latency and optimizes the available memory and bus bandwidth.


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