Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Patent
1996-12-09
1998-06-09
Lane, Jack A.
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
711157, G06F 1200
Patent
active
057651825
ABSTRACT:
This invention relates to an improved memory storage system which allows interleaving between two separate memory banks. In this way, data can be retrieved simultaneously from the two memory banks and placed on the data bus alternately. While the data from one data bank is on the data bus, data is being retrieved from the other data bank. In general, a data bank requires a number of wait states in order to retrieve data, during which no data is transferred onto the data bus from that particular data bank. However, by interleaving the data between two separate memory banks, data retrieved from the first memory bank can be placed on the data bus while the second memory bank is undergoing several wait states retrieving the next group of data. In this way, data is continuously placed on the data bus and the number of wait states during which no data is present on the data bus are decreased, preferably to zero. In one embodiment, the memory banks are on separate boards with separate buffers on each board for interfacing each memory bank with the data bus, and, a memory controller, separate from the buffers, selects both buffers when interleaving data between the memory banks on the two boards.
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HT352 -Bus Control Unit -Preliminary Specification Jul. 18, 1994; Version 0.22.
HT355 -ECC and Data Pipeline -Preliminary Version Jul. 11, 1994; Version 0.22.
Banerjee Kaberi
Lau Winnie K.W.
Lane Jack A.
LSI Logic Corporation
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