Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Patent
1996-06-28
1998-06-02
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
711158, 711163, 711161, 711153, 711152, 711127, 711131, 711 5, G06F 1200
Patent
active
057617325
ABSTRACT:
A method and apparatus for interfacing a memory card with a system having a smaller bus width while maintaining its interchangeability with other systems having larger bus widths. The host accesses data stored in the memory card using an interleaving scheme, such as a two-way interleaving scheme. The host provides a first enable signal and a second enable signal. In response to the first enable signal, data is accessed from a first section of the addressed memory location, and in response to the second enable signal, data is accessed from a second section of the addressed memory location. The first section of the addressed memory location may store even data bytes and the second section of the addressed memory location may store odd data bytes. The host may only access one section of the selected memory location at a time when using the interleaving scheme.
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Casey Sean
Shaberman Tony
Intel Corporation
Swann Tod R.
Tzeng Fred Fei
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