Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2007-04-03
2007-04-03
Chung, Phung My (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S786000, C714S758000, C714S790000
Reexamination Certificate
active
10324215
ABSTRACT:
In an apparatus for data transmission in a communication system, a turbo encoder encodes data bits to generate systematic bits and parity bits, and a rate matcher matches the systematic bits and parity bits. A first interleaver writes the rate-matched systematic bits on a row by row basis, and performs inter-column permutation. A second interleaver writes the rate-matched parity bits on a row-by-row basis, and performs inter-column permutation. A modulator alternatively collects the permutated bits on a column by column basis from the first and second interleavers, and maps collected bits from the first and second interleavers onto one modulation symbol, wherein a size of the first interleaver is equal to a size of the second interleaver.
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Choi Gin-Kyu
Kim Hun-Kee
Kim Noh-Sun
Lee Jun-Sung
Moon Yong-Suk
Chung Phung My
The Farrell Law Firm
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