Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2005-01-18
2005-01-18
Dildine, R. Stephen (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
06845482
ABSTRACT:
Techniques to efficiently generate memory addresses for a Turbo code interleaver using a number of look-up tables. An interleaver includes a storage unit, sets of tables, and an address generator. The storage unit stores K elements for a data packet at locations representative of an R×C array, with the elements being stored in a first (e.g., linear) order and provided in a second (e.g., interleaved) order. A first set of table(s) stores sequences (e.g., inter-row permutation sequences PA, PB, PC, and PD) used to perform row permutation of the array to map from the first order to the second order. A second set of table(s) stores sequences (e.g., intra-row base sequences and prime number sequences) used to perform column permutation. The address generator receives a first address for the first order and generates a corresponding second address for the second order based on sequences stored in the tables.
REFERENCES:
A unified turbo/Viterbi channel decoder for 3GPP mobile wireless in 0.18-/spl mu/m CMOS; Bickerstaff, M.A et al.; Solid-State Circuits, IEEE Journal of, vol.: 37 , Issue: 11 , Nov. 2002; pp.: 1555-1564.*
3rdGeneration Partnership Project; Technical Specification Group Radio Access Network; Multiplexing and channel coding (FDD) Jun. 2000, pp. 1-62.
Barbulescu et al. Turbo Codes: a tutorial on a new class of powerful error correcting coding schemes. XP-002215242, pp. 1-48 (1999).
Shiu Da-Shan
Yao Iwen
Brown Charles D
Dildine R. Stephen
Pappas George C.
Qualcomm Incorporated
Wadsworth Philip R
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