Interleaver and device for decoding digital signals...

Details Interleaver and device for decoding digital signals... Interleaver and device for decoding digital signals...

2007-12-11

2007-12-11

Chase, Shelly (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Data formatting to improve error detection correction...

Reexamination Certificate

active

10880334

ABSTRACT:
An interleaver includes two random access memories for storing data and an addressing device (100) linked to respective address inputs of the two memories. The addressing device is designed to transmit, at each instant of a clock, a cue for read access to one of the two memories and a cue for write access to the other of the two memories, so that, at each instant, a data item is written to or read from each memory.

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Wu, et al., “Implementation of Low Complexity, Low Power, Integer-Based Turbo Decoder”, Globcom '01, 2001 IEEE Gobal Telecommunications Conference, San Antonio, TX, Nov. 25-29, 2001, IEEE, New York, vol. 2 of 6, Nov. 25, 2001, pp. 946-951, XP001099245.
Preliminary French Search Report, FR 03 08238, dated Oct. 29, 2003.

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